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Author: AZero13

llvm/test/CodeGen/ARM/combine-movc-sub.ll

@@ -25,15 +25,15 @@ declare void @foo(ptr, ptr)
 define hidden fastcc ptr @test(ptr %Search, ptr %ClauseList, i32 %Level, ptr nocapture %New) {
 ; CHECK-LABEL: test:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    push.w {r4, r5, r6, r7, r8, r9, lr}
-; CHECK-NEXT:    sub sp, #4
-; CHECK-NEXT:    sub.w r7, r2, #32
+; CHECK-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, lr}
+; CHECK-NEXT:    sub.w r9, r2, #32
 ; CHECK-NEXT:    mov r8, r0
 ; CHECK-NEXT:    movs r0, #1
 ; CHECK-NEXT:    mov r4, r2
-; CHECK-NEXT:    add.w r6, r0, r7, lsr #5
+; CHECK-NEXT:    add.w r6, r0, r9, lsr #5
 ; CHECK-NEXT:    mov r5, r1
-; CHECK-NEXT:    mov.w r9, #0
+; CHECK-NEXT:    lsr.w r7, r9, #5
+; CHECK-NEXT:    mov.w r10, #0
 ; CHECK-NEXT:    b .LBB0_2
 ; CHECK-NEXT:  .LBB0_1: @ %for.inc
 ; CHECK-NEXT:    @ in Loop: Header=BB0_2 Depth=1
@@ -47,15 +47,15 @@ define hidden fastcc ptr @test(ptr %Search, ptr %ClauseList, i32 %Level, ptr noc
 ; CHECK-NEXT:    add.w r0, r0, r6, lsl #2
 ; CHECK-NEXT:    ldr r0, [r0, #40]
 ; CHECK-NEXT:    it hi
-; CHECK-NEXT:    andhi r2, r7, #31
+; CHECK-NEXT:    subhi.w r2, r9, r7, lsl #5
 ; CHECK-NEXT:    lsrs r0, r2
 ; CHECK-NEXT:    lsls r0, r0, #31
 ; CHECK-NEXT:    beq .LBB0_1
 ; CHECK-NEXT:  @ %bb.3: @ %if.then
 ; CHECK-NEXT:    @ in Loop: Header=BB0_2 Depth=1
 ; CHECK-NEXT:    mov r0, r8
 ; CHECK-NEXT:    bl foo
-; CHECK-NEXT:    str.w r9, [r5, #4]
+; CHECK-NEXT:    str.w r10, [r5, #4]
 ; CHECK-NEXT:    b .LBB0_1
 entry:
   %cmp4.i.i = icmp ugt i32 %Level, 31

llvm/test/CodeGen/ARM/dagcombine-ld-op-st.ll

@@ -41,10 +41,11 @@ define i16 @test(ptr %p1) {
 ;
 ; CHECK-BE-NORMAL-LABEL: test:
 ; CHECK-BE-NORMAL:       @ %bb.0: @ %entry
-; CHECK-BE-NORMAL-NEXT:    ldrh r1, [r0]
+; CHECK-BE-NORMAL-NEXT:    ldr r1, [r0]
 ; CHECK-BE-NORMAL-NEXT:    movw r2, #65534
-; CHECK-BE-NORMAL-NEXT:    orr r1, r1, r2
-; CHECK-BE-NORMAL-NEXT:    strh r1, [r0]
+; CHECK-BE-NORMAL-NEXT:    orr r2, r2, r1, lsr #16
+; CHECK-BE-NORMAL-NEXT:    pkhbt r1, r1, r2, lsl #16
+; CHECK-BE-NORMAL-NEXT:    str r1, [r0]
 ; CHECK-BE-NORMAL-NEXT:    mov r0, #0
 ; CHECK-BE-NORMAL-NEXT:    bx lr
 ;

llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll

@@ -90,16 +90,16 @@ define void @i56_or(ptr %a) {
 ;
 ; BE-LABEL: i56_or:
 ; BE:       @ %bb.0:
-; BE-NEXT:    mov r1, r0
-; BE-NEXT:    ldr r0, [r0]
-; BE-NEXT:    ldrh r2, [r1, #4]!
-; BE-NEXT:    ldrb r3, [r1, #2]
+; BE-NEXT:    ldr r1, [r0]
+; BE-NEXT:    strb r1, [r0, #3]
+; BE-NEXT:    ldrh r2, [r0, #4]!
+; BE-NEXT:    ldrb r3, [r0, #2]
 ; BE-NEXT:    orr r2, r3, r2, lsl #8
-; BE-NEXT:    orr r0, r2, r0, lsl #24
-; BE-NEXT:    orr r0, r0, #384
-; BE-NEXT:    strb r0, [r1, #2]
-; BE-NEXT:    lsr r0, r0, #8
-; BE-NEXT:    strh r0, [r1]
+; BE-NEXT:    orr r1, r2, r1, lsl #24
+; BE-NEXT:    orr r1, r1, #384
+; BE-NEXT:    strb r1, [r0, #2]
+; BE-NEXT:    lsr r1, r1, #8
+; BE-NEXT:    strh r1, [r0]
 ; BE-NEXT:    mov pc, lr
   %aa = load i56, ptr %a
   %b = or i56 %aa, 384
@@ -118,11 +118,14 @@ define void @i56_and_or(ptr %a) {
 ;
 ; BE-LABEL: i56_and_or:
 ; BE:       @ %bb.0:
-; BE-NEXT:    ldrh r1, [r0, #4]!
-; BE-NEXT:    mov r2, #128
-; BE-NEXT:    orr r1, r1, #1
-; BE-NEXT:    strb r2, [r0, #2]
-; BE-NEXT:    strh r1, [r0]
+; BE-NEXT:    mov r1, r0
+; BE-NEXT:    mov r3, #128
+; BE-NEXT:    ldrh r2, [r1, #4]!
+; BE-NEXT:    strb r3, [r1, #2]
+; BE-NEXT:    ldr r3, [r0]
+; BE-NEXT:    strb r3, [r0, #3]
+; BE-NEXT:    orr r0, r2, #1
+; BE-NEXT:    strh r0, [r1]
 ; BE-NEXT:    mov pc, lr
 
   %b = load i56, ptr %a, align 1
@@ -143,9 +146,11 @@ define void @i56_insert_bit(ptr %a, i1 zeroext %bit) {
 ;
 ; BE-LABEL: i56_insert_bit:
 ; BE:       @ %bb.0:
-; BE-NEXT:    ldrh r2, [r0, #4]!
+; BE-NEXT:    ldr r2, [r0]
 ; BE-NEXT:    mov r3, #57088
+; BE-NEXT:    strb r2, [r0, #3]
 ; BE-NEXT:    orr r3, r3, #16711680
+; BE-NEXT:    ldrh r2, [r0, #4]!
 ; BE-NEXT:    and r2, r3, r2, lsl #8
 ; BE-NEXT:    orr r1, r2, r1, lsl #13
 ; BE-NEXT:    lsr r1, r1, #8

llvm/test/CodeGen/ARM/rotate-add.ll

@@ -124,9 +124,9 @@ define i64 @test_rotl_udiv_special_case(i64 %i) {
 ; CHECK-NEXT:    ldr r12, .LCPI8_0
 ; CHECK-NEXT:    adc lr, r2, #0
 ; CHECK-NEXT:    umull r3, r2, lr, r12
-; CHECK-NEXT:    bic r3, r2, #1
-; CHECK-NEXT:    add r2, r3, r2, lsr #1
 ; CHECK-NEXT:    ldr r3, .LCPI8_1
+; CHECK-NEXT:    lsr r2, r2, #1
+; CHECK-NEXT:    add r2, r2, r2, lsl #1
 ; CHECK-NEXT:    sub r2, lr, r2
 ; CHECK-NEXT:    subs r0, r0, r2
 ; CHECK-NEXT:    sbc r1, r1, #0