[RISCV] Add compress patterns for qc.extu and qc.mveqi

Change-Id: If45e95ffb225e058652f6528e46b5cb7b924832f

Author: hchandel

llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

@@ -42,11 +42,10 @@ def uimm5_plus1 : RISCVOp, ImmLeaf<XLenVT,
   let OperandType = "OPERAND_UIMM5_PLUS1";
   let MCOperandPredicate = [{
     int64_t Imm;
-    if (MCOp.evaluateAsConstantImm(Imm))
-      return (isUInt<5>(Imm) && (Imm != 0)) || (Imm == 32);
-    return MCOp.isBareSymbolRef();
+    if (!MCOp.evaluateAsConstantImm(Imm))
+      return false;
+    return (isUInt<5>(Imm) && (Imm != 0)) || (Imm == 32);
   }];
-
 }
 
 def uimm5ge6_plus1 : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
@@ -57,9 +56,9 @@ def uimm5ge6_plus1 : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
   let OperandType = "OPERAND_UIMM5_GE6_PLUS1";
   let MCOperandPredicate = [{
     int64_t Imm;
-    if (MCOp.evaluateAsConstantImm(Imm))
-      return (Imm >= 6) && (isUInt<5>(Imm) || (Imm == 32));
-    return MCOp.isBareSymbolRef();
+    if (!MCOp.evaluateAsConstantImm(Imm))
+      return false;
+    return (Imm >= 6) && (isUInt<5>(Imm) || (Imm == 32));
   }];
 }