[AMDGPU] Update lit test.

Author: harrisonGPU

llvm/test/CodeGen/AMDGPU/amdpal.ll

@@ -56,7 +56,13 @@ entry:
 ; disappear.
 
 ; PAL-LABEL: {{^}}scratch2_cs:
-; PAL: buffer_store{{.*}}, s[[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}
+; PAL-NEXT: ; %bb.0:
+; PAL-NEXT: v_add_i32_e32 v0, vcc, 1, v6
+; PAL-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; PAL-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
+; PAL-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0
+; PAL-NEXT: v_cndmask_b32_e32 v0, v1, v4, vcc
+; PAL-NEXT: buffer_store{{.*}}, s[[[SCRATCHDESC]]:
 
 define amdgpu_cs void @scratch2_cs(i32 inreg, i32 inreg, i32 inreg, <3 x i32> inreg, i32 inreg, <3 x i32> %coord, <2 x i32> %in, i32 %extra, i32 %idx) #0 {
 entry:

llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep-of-gep.ll

@@ -1,6 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
 ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s
-target triple = "amdgcn-amd-amdhsa"
 define amdgpu_ps void @scalar_alloca_ptr_with_vector_gep_of_gep(i32 %j) #0 {
 ; CHECK-LABEL: define amdgpu_ps void @scalar_alloca_ptr_with_vector_gep_of_gep(
 ; CHECK-SAME: i32 [[J:%.*]]) #[[ATTR0:[0-9]+]] {
@@ -14,28 +13,28 @@ define amdgpu_ps void @scalar_alloca_ptr_with_vector_gep_of_gep(i32 %j) #0 {
 ;
 entry:
   %SortedFragments = alloca [10 x <2 x i32>], align 8, addrspace(5)
-  %0 = getelementptr [10 x <2 x i32>], ptr addrspace(5) %SortedFragments, i32 0, i32 %j
-  %1 = getelementptr i8, ptr addrspace(5) %0, i32 4
-  %2 = load i32, ptr addrspace(5) %1, align 4
+  %row = getelementptr [10 x <2 x i32>], ptr addrspace(5) %SortedFragments, i32 0, i32 %j
+  %elt1 = getelementptr i8, ptr addrspace(5) %row, i32 4
+  %val = load i32, ptr addrspace(5) %elt1, align 4
   ret void
 }
 
 attributes #0 = { "amdgpu-promote-alloca-to-vector-max-regs"="32" }
 
-define amdgpu_cs void @scalar_alloca_ptr_with_vector_gep_of_scratch(i32 inreg, i32 inreg, i32 inreg, <3 x i32> inreg, i32 inreg, <3 x i32> %coord, <2 x i32> %in, i32 %extra, i32 %idx) #1 {
+define amdgpu_cs void @scalar_alloca_ptr_with_vector_gep_of_scratch(i32 inreg %0, i32 inreg %1, i32 inreg %2, <3 x i32> inreg %coord, i32 inreg %4, <3 x i32> %v_in, <2 x i32> %in, i32 %extra, i32 %idx, ptr addrspace(8) %buffer) #0 {
 ; CHECK-LABEL: define amdgpu_cs void @scalar_alloca_ptr_with_vector_gep_of_scratch(
-; CHECK-SAME: i32 inreg [[TMP0:%.*]], i32 inreg [[TMP1:%.*]], i32 inreg [[TMP2:%.*]], <3 x i32> inreg [[TMP3:%.*]], i32 inreg [[TMP4:%.*]], <3 x i32> [[COORD:%.*]], <2 x i32> [[IN:%.*]], i32 [[EXTRA:%.*]], i32 [[IDX:%.*]]) #[[ATTR1:[0-9]+]] {
+; CHECK-SAME: i32 inreg [[TMP0:%.*]], i32 inreg [[TMP1:%.*]], i32 inreg [[TMP2:%.*]], <3 x i32> inreg [[COORD:%.*]], i32 inreg [[TMP3:%.*]], <3 x i32> [[V_IN:%.*]], <2 x i32> [[IN:%.*]], i32 [[EXTRA:%.*]], i32 [[IDX:%.*]], ptr addrspace(8) [[BUFFER:%.*]]) #[[ATTR0]] {
 ; CHECK-NEXT:  [[ENTRY:.*:]]
 ; CHECK-NEXT:    [[V:%.*]] = freeze <3 x i32> poison
-; CHECK-NEXT:    [[TMP5:%.*]] = insertelement <3 x i32> [[V]], i32 [[EXTRA]], i32 0
-; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x i32> [[IN]], i64 0
-; CHECK-NEXT:    [[TMP7:%.*]] = insertelement <3 x i32> [[TMP5]], i32 [[TMP6]], i32 1
-; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <2 x i32> [[IN]], i64 1
-; CHECK-NEXT:    [[TMP9:%.*]] = insertelement <3 x i32> [[TMP7]], i32 [[TMP8]], i32 2
-; CHECK-NEXT:    [[TMP10:%.*]] = add i32 1, [[IDX]]
-; CHECK-NEXT:    [[TMP11:%.*]] = extractelement <3 x i32> [[TMP9]], i32 [[TMP10]]
-; CHECK-NEXT:    [[XF:%.*]] = bitcast i32 [[TMP11]] to float
-; CHECK-NEXT:    call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float [[XF]], ptr addrspace(8) poison, i32 0, i32 0, i32 0)
+; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <3 x i32> [[V]], i32 [[EXTRA]], i32 0
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <2 x i32> [[IN]], i64 0
+; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <3 x i32> [[TMP4]], i32 [[TMP5]], i32 1
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <2 x i32> [[IN]], i64 1
+; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <3 x i32> [[TMP6]], i32 [[TMP7]], i32 2
+; CHECK-NEXT:    [[TMP9:%.*]] = add i32 1, [[IDX]]
+; CHECK-NEXT:    [[TMP10:%.*]] = extractelement <3 x i32> [[TMP8]], i32 [[TMP9]]
+; CHECK-NEXT:    [[XF:%.*]] = bitcast i32 [[TMP10]] to float
+; CHECK-NEXT:    store float [[XF]], ptr addrspace(8) [[BUFFER]], align 4
 ; CHECK-NEXT:    ret void
 ;
 entry:
@@ -46,10 +45,6 @@ entry:
   %e = getelementptr [2 x i32], ptr addrspace(5) %v1, i32 0, i32 %idx
   %x = load i32, ptr addrspace(5) %e
   %xf = bitcast i32 %x to float
-  call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float %xf, ptr addrspace(8) poison, i32 0, i32 0, i32 0)
+  store float %xf, ptr addrspace(8) %buffer, align 4
   ret void
 }
-
-attributes #1 = { nounwind "amdgpu-git-ptr-high"="0x1234" }
-
-declare void @llvm.amdgcn.raw.ptr.buffer.store.f32(float, ptr addrspace(8), i32, i32, i32 immarg)