Rebase

Created using spr 1.3.6-beta.1

Author: ilovepi

clang/test/Driver/print-supported-cpus-aarch64.c

@@ -0,0 +1,27 @@
+// Test that --print-supported-cpus lists supported CPU models, including aliases.
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang --target=arm64-apple-macosx --print-supported-cpus 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK --implicit-check-not=apple-latest
+
+// CHECK: Target: arm64-apple-macosx
+
+// CHECK: apple-a11
+// CHECK: apple-a12
+// CHECK: apple-a13
+// CHECK: apple-a14
+// CHECK: apple-a15
+// CHECK: apple-a16
+// CHECK: apple-a17
+// CHECK: apple-a7
+// CHECK: apple-a8
+// CHECK: apple-a9
+// CHECK: apple-m1
+// CHECK: apple-m2
+// CHECK: apple-m3
+// CHECK: apple-m4
+// CHECK: apple-s4
+// CHECK: apple-s5
+
+// CHECK: Use -mcpu or -mtune to specify the target's processor.

compiler-rt/lib/interception/interception_win.cpp

@@ -634,6 +634,9 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
     case 0xD284:  // 84 D2 : test dl,dl
       return 2;
 
+    case 0xC1F6:  // F6 C1 XX : test cl, XX
+      return 3;
+
     // Cannot overwrite control-instruction. Return 0 to indicate failure.
     case 0x25FF:  // FF 25 XX YY ZZ WW : jmp dword ptr ds:[WWZZYYXX]
       return 0;
@@ -723,8 +726,7 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
       return 7;
   }
 
-  switch (0x00FFFFFF & *(u32*)address) {
-    case 0x07c1f6:    // f6 c1 07 : test cl, 0x7
+  switch (0x00FFFFFF & *(u32 *)address) {
     case 0x10b70f:    // 0f b7 10 : movzx edx, WORD PTR [rax]
     case 0xc00b4d:    // 4d 0b c0 : or r8, r8
     case 0xc03345:    // 45 33 c0 : xor r8d, r8d
@@ -808,7 +810,6 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
     case 0x798141:  // 41 81 79 XX YY YY YY YY : cmp DWORD PTR [r9+YY], XX XX XX XX
     case 0x7a8141:  // 41 81 7a XX YY YY YY YY : cmp DWORD PTR [r10+YY], XX XX XX XX
     case 0x7b8141:  // 41 81 7b XX YY YY YY YY : cmp DWORD PTR [r11+YY], XX XX XX XX
-    case 0x7c8141:  // 41 81 7c XX YY YY YY YY : cmp DWORD PTR [r12+YY], XX XX XX XX
     case 0x7d8141:  // 41 81 7d XX YY YY YY YY : cmp DWORD PTR [r13+YY], XX XX XX XX
     case 0x7e8141:  // 41 81 7e XX YY YY YY YY : cmp DWORD PTR [r14+YY], XX XX XX XX
     case 0x7f8141:  // 41 81 7f YY XX XX XX XX : cmp DWORD PTR [r15+YY], XX XX XX XX
@@ -835,6 +836,10 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
     case 0x2444c7:    // C7 44 24 XX YY YY YY YY
                       //   mov dword ptr [rsp + XX], YYYYYYYY
       return 8;
+
+    case 0x7c8141:  // 41 81 7c ZZ YY XX XX XX XX
+                    // cmp DWORD PTR [reg+reg*n+YY], XX XX XX XX
+      return 9;
   }
 
   switch (*(u32*)(address)) {

compiler-rt/lib/interception/tests/interception_win_test.cpp

@@ -927,6 +927,7 @@ const struct InstructionSizeData {
     { 3, {0x4d, 0x85, 0xed}, 0, "4d 85 ed : test r13, r13"},
     { 3, {0x4d, 0x85, 0xf6}, 0, "4d 85 f6 : test r14, r14"},
     { 3, {0x4d, 0x85, 0xff}, 0, "4d 85 ff : test r15, r15"},
+    { 3, {0xf6, 0xc1, 0x72}, 0, "f6 c1 XX : test cl, XX"},
     { 4, {0x44, 0x0f, 0xb6, 0x1a}, 0, "44 0f b6 1a : movzx r11d, BYTE PTR [rdx]"},
     { 4, {0x44, 0x8d, 0x42, 0x73}, 0, "44 8d 42 XX : lea r8d , [rdx + XX]"},
     { 4, {0x48, 0x83, 0xec, 0x73}, 0, "48 83 ec XX : sub rsp, XX"},
@@ -989,6 +990,7 @@ const struct InstructionSizeData {
     { 8, {0x41, 0x81, 0x7f, 0x73, 0x74, 0x75, 0x76, 0x77}, 0, "41 81 7f YY XX XX XX XX : cmp DWORD PTR [r15+YY], XX XX XX XX"},
     { 8, {0x81, 0x7c, 0x24, 0x73, 0x74, 0x75, 0x76, 0x77}, 0, "81 7c 24 YY XX XX XX XX : cmp DWORD PTR [rsp+YY], XX XX XX XX"},
     { 8, {0xc7, 0x44, 0x24, 0x73, 0x74, 0x75, 0x76, 0x77}, 0, "C7 44 24 XX YY YY YY YY : mov dword ptr [rsp + XX], YYYYYYYY"},
+    { 9, {0x41, 0x81, 0x7c, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78}, 0, "41 81 7c ZZ YY XX XX XX XX : cmp DWORD PTR [reg+reg*n+YY], XX XX XX XX"},
     { 9, {0xA1, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78}, 0, "A1 XX XX XX XX XX XX XX XX : movabs eax, dword ptr ds:[XXXXXXXX]"},
 #else
     // sorted list

flang/Maintainers.md

@@ -0,0 +1,95 @@
+# Flang maintainers
+
+This file is a list of the
+[maintainers](https://llvm.org/docs/DeveloperPolicy.html#maintainers) for
+Flang
+
+## Active maintainers
+
+### Lead maintainers
+The following people are the active maintainers for the project. Please reach
+out to them for code reviews, questions about their area of expertise, or other
+assistance.
+
+#### All areas not covered by others
+Steve Scalpone \
+[email protected] (email), sscalpone (GitHub), sscalpone (Discourse)
+
+####  Backend (Lowering, Fortran dialects, Codegen)
+Jean Perier \
+[email protected] (email), jeanPerier (GitHub), jeanPerier (Discourse)
+
+### Component maintainers
+These maintainers are responsible for particular high-level components within
+Flang that are typically contained to one area of the compiler.
+
+#### Driver
+Andrzej Warzyński \
+[email protected] (email), banach-space (GitHub), banach-space (Discourse)
+
+Tarun Prabhu \
+[email protected] (email), tarunprabhu (GitHub), tarunprabhu (Discourse)
+
+#### Alias Analysis
+Renaud Kauffmann \
+[email protected] (email), Renaud-K (GitHub), Renaud-K (Discourse)
+
+#### PFT, Block, IEEE support
+Val Donaldson \
+[email protected] (email), vdonaldson (GitHub)
+
+#### Lowering, HLFIR, FIR, Codegen
+Jean Perier \
+[email protected] (email), jeanPerier (GitHub), jeanPerier (Discourse)
+
+Slava Zakharin \
+[email protected] (email), vzakhari (GitHub), szakharin (Discourse)
+
+Tom Eccles \
+[email protected] (email), tblah (GitHub), tblah (Discourse)
+
+Valentin Clement \
+[email protected] (email), clementval (GitHub), clementval (Discourse)
+
+#### OpenMP
+##### CPU support
+Tom Eccles \
+[email protected] (email), tblah (GitHub), tblah (Discourse)
+
+##### OpenMP 6.0
+Krzysztof Parzyszek \
+[email protected] (email), kparzysz (GitHub), kparzysz (Discourse)
+
+##### Target Offload
+Sergio Afonso \
+[email protected] (email), skatrak (GitHub), skatrak (Discourse) 
+
+#### OpenACC
+Valentin Clement \
+[email protected] (email), clementval (GitHub), clementval (Discourse)
+
+Razvan Lupusoru \
+[email protected] (email), razvanlupusoru (GitHub), razvan.lupusoru (Discourse)
+
+#### CUDA Fortran
+Valentin Clement \
+[email protected] (email), clementval (GitHub), clementval (Discourse)
+
+#### Debug
+Abid Qadeer \
+[email protected] (email), abidh (GitHub), abidh (Discourse)
+
+## Inactive Maintainers
+### Lead Maintainers
+#### Backend : (Lowering, FIR, Codegen)
+Eric Schweitz \
+[email protected] (email), schweitzpgi (GitHub), schweitz (Discourse)
+
+### Component Maintainers
+#### Semantics
+Tim Keith
+
+#### OpenMP
+Kiran Chandramohan \
+[email protected] (email), kiranchandramohan (GitHub),  kiranchandramohan (Discourse)
+

flang/Maintainers.txt

@@ -63,7 +63,8 @@ class Triple;
 class TargetSubtargetInfo : public MCSubtargetInfo {
 protected: // Can only create subclasses...
   TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU,
-                      StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
+                      StringRef FS, ArrayRef<StringRef> PN,
+                      ArrayRef<SubtargetFeatureKV> PF,
                       ArrayRef<SubtargetSubTypeKV> PD,
                       const MCWriteProcResEntry *WPR,
                       const MCWriteLatencyEntry *WL,

llvm/include/llvm/CodeGen/TargetSubtargetInfo.h

@@ -77,6 +77,7 @@ class MCSubtargetInfo {
   Triple TargetTriple;
   std::string CPU; // CPU being targeted.
   std::string TuneCPU; // CPU being tuned for.
+  ArrayRef<StringRef> ProcNames; // Processor list, including aliases
   ArrayRef<SubtargetFeatureKV> ProcFeatures;  // Processor feature list
   ArrayRef<SubtargetSubTypeKV> ProcDesc;  // Processor descriptions
 
@@ -95,7 +96,8 @@ class MCSubtargetInfo {
 public:
   MCSubtargetInfo(const MCSubtargetInfo &) = default;
   MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU,
-                  StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
+                  StringRef FS, ArrayRef<StringRef> PN,
+                  ArrayRef<SubtargetFeatureKV> PF,
                   ArrayRef<SubtargetSubTypeKV> PD,
                   const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
                   const MCReadAdvanceEntry *RA, const InstrStage *IS,

llvm/include/llvm/MC/MCSubtargetInfo.h

@@ -16,11 +16,12 @@ using namespace llvm;
 
 TargetSubtargetInfo::TargetSubtargetInfo(
     const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
-    ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetSubTypeKV> PD,
-    const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
-    const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC,
-    const unsigned *FP)
-    : MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) {}
+    ArrayRef<StringRef> PN, ArrayRef<SubtargetFeatureKV> PF,
+    ArrayRef<SubtargetSubTypeKV> PD, const MCWriteProcResEntry *WPR,
+    const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
+    const InstrStage *IS, const unsigned *OC, const unsigned *FP)
+    : MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, WPR, WL, RA, IS, OC,
+                      FP) {}
 
 TargetSubtargetInfo::~TargetSubtargetInfo() = default;
 

llvm/lib/CodeGen/TargetSubtargetInfo.cpp

@@ -85,16 +85,22 @@ static void ApplyFeatureFlag(FeatureBitset &Bits, StringRef Feature,
 }
 
 /// Return the length of the longest entry in the table.
-template <typename T>
-static size_t getLongestEntryLength(ArrayRef<T> Table) {
+static size_t getLongestEntryLength(ArrayRef<SubtargetFeatureKV> Table) {
   size_t MaxLen = 0;
   for (auto &I : Table)
     MaxLen = std::max(MaxLen, std::strlen(I.Key));
   return MaxLen;
 }
 
+static size_t getLongestEntryLength(ArrayRef<StringRef> Table) {
+  size_t MaxLen = 0;
+  for (StringRef I : Table)
+    MaxLen = std::max(MaxLen, I.size());
+  return MaxLen;
+}
+
 /// Display help for feature and mcpu choices.
-static void Help(ArrayRef<SubtargetSubTypeKV> CPUTable,
+static void Help(ArrayRef<StringRef> CPUNames,
                  ArrayRef<SubtargetFeatureKV> FeatTable) {
   // the static variable ensures that the help information only gets
   // printed once even though a target machine creates multiple subtargets
@@ -104,14 +110,20 @@ static void Help(ArrayRef<SubtargetSubTypeKV> CPUTable,
   }
 
   // Determine the length of the longest CPU and Feature entries.
-  unsigned MaxCPULen  = getLongestEntryLength(CPUTable);
+  unsigned MaxCPULen = getLongestEntryLength(CPUNames);
   unsigned MaxFeatLen = getLongestEntryLength(FeatTable);
 
   // Print the CPU table.
   errs() << "Available CPUs for this target:\n\n";
-  for (auto &CPU : CPUTable)
-    errs() << format("  %-*s - Select the %s processor.\n", MaxCPULen, CPU.Key,
-                     CPU.Key);
+  for (auto &CPUName : CPUNames) {
+    // Skip apple-latest, as that's only meant to be used in
+    // disassemblers/debuggers, and we don't want normal code to be built with
+    // it as an -mcpu=
+    if (CPUName == "apple-latest")
+      continue;
+    errs() << format("  %-*s - Select the %s processor.\n", MaxCPULen,
+                     CPUName.str().c_str(), CPUName.str().c_str());
+  }
   errs() << '\n';
 
   // Print the Feature table.
@@ -127,7 +139,7 @@ static void Help(ArrayRef<SubtargetSubTypeKV> CPUTable,
 }
 
 /// Display help for mcpu choices only
-static void cpuHelp(ArrayRef<SubtargetSubTypeKV> CPUTable) {
+static void cpuHelp(ArrayRef<StringRef> CPUNames) {
   // the static variable ensures that the help information only gets
   // printed once even though a target machine creates multiple subtargets
   static bool PrintOnce = false;
@@ -137,8 +149,14 @@ static void cpuHelp(ArrayRef<SubtargetSubTypeKV> CPUTable) {
 
   // Print the CPU table.
   errs() << "Available CPUs for this target:\n\n";
-  for (auto &CPU : CPUTable)
-    errs() << "\t" << CPU.Key << "\n";
+  for (auto &CPU : CPUNames) {
+    // Skip apple-latest, as that's only meant to be used in
+    // disassemblers/debuggers, and we don't want normal code to be built with
+    // it as an -mcpu=
+    if (CPU == "apple-latest")
+      continue;
+    errs() << "\t" << CPU << "\n";
+  }
   errs() << '\n';
 
   errs() << "Use -mcpu or -mtune to specify the target's processor.\n"
@@ -148,7 +166,9 @@ static void cpuHelp(ArrayRef<SubtargetSubTypeKV> CPUTable) {
   PrintOnce = true;
 }
 
-static FeatureBitset getFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS,
+static FeatureBitset getFeatures(MCSubtargetInfo &STI, StringRef CPU,
+                                 StringRef TuneCPU, StringRef FS,
+                                 ArrayRef<StringRef> ProcNames,
                                  ArrayRef<SubtargetSubTypeKV> ProcDesc,
                                  ArrayRef<SubtargetFeatureKV> ProcFeatures) {
   SubtargetFeatures Features(FS);
@@ -163,7 +183,7 @@ static FeatureBitset getFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS,
 
   // Check if help is needed
   if (CPU == "help")
-    Help(ProcDesc, ProcFeatures);
+    Help(ProcNames, ProcFeatures);
 
   // Find CPU entry if CPU name is specified.
   else if (!CPU.empty()) {
@@ -196,9 +216,9 @@ static FeatureBitset getFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS,
   for (const std::string &Feature : Features.getFeatures()) {
     // Check for help
     if (Feature == "+help")
-      Help(ProcDesc, ProcFeatures);
+      Help(ProcNames, ProcFeatures);
     else if (Feature == "+cpuhelp")
-      cpuHelp(ProcDesc);
+      cpuHelp(ProcNames);
     else
       ApplyFeatureFlag(Bits, Feature, ProcFeatures);
   }
@@ -208,7 +228,8 @@ static FeatureBitset getFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS,
 
 void MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef TuneCPU,
                                           StringRef FS) {
-  FeatureBits = getFeatures(CPU, TuneCPU, FS, ProcDesc, ProcFeatures);
+  FeatureBits =
+      getFeatures(*this, CPU, TuneCPU, FS, ProcNames, ProcDesc, ProcFeatures);
   FeatureString = std::string(FS);
 
   if (!TuneCPU.empty())
@@ -219,20 +240,19 @@ void MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef TuneCPU,
 
 void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef TuneCPU,
                                          StringRef FS) {
-  FeatureBits = getFeatures(CPU, TuneCPU, FS, ProcDesc, ProcFeatures);
+  FeatureBits =
+      getFeatures(*this, CPU, TuneCPU, FS, ProcNames, ProcDesc, ProcFeatures);
   FeatureString = std::string(FS);
 }
 
-MCSubtargetInfo::MCSubtargetInfo(const Triple &TT, StringRef C, StringRef TC,
-                                 StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
-                                 ArrayRef<SubtargetSubTypeKV> PD,
-                                 const MCWriteProcResEntry *WPR,
-                                 const MCWriteLatencyEntry *WL,
-                                 const MCReadAdvanceEntry *RA,
-                                 const InstrStage *IS, const unsigned *OC,
-                                 const unsigned *FP)
+MCSubtargetInfo::MCSubtargetInfo(
+    const Triple &TT, StringRef C, StringRef TC, StringRef FS,
+    ArrayRef<StringRef> PN, ArrayRef<SubtargetFeatureKV> PF,
+    ArrayRef<SubtargetSubTypeKV> PD, const MCWriteProcResEntry *WPR,
+    const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
+    const InstrStage *IS, const unsigned *OC, const unsigned *FP)
     : TargetTriple(TT), CPU(std::string(C)), TuneCPU(std::string(TC)),
-      ProcFeatures(PF), ProcDesc(PD), WriteProcResTable(WPR),
+      ProcNames(PN), ProcFeatures(PF), ProcDesc(PD), WriteProcResTable(WPR),
       WriteLatencyTable(WL), ReadAdvanceTable(RA), Stages(IS),
       OperandCycles(OC), ForwardingPaths(FP) {
   InitMCProcessorInfo(CPU, TuneCPU, FS);