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[X86][AMX] Support AMX-FP8 (#113850)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
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‎clang/docs/ReleaseNotes.rst

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@@ -661,6 +661,7 @@ X86 Support
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- Supported intrinsics for ``MOVRS AND AVX10.2``.
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* Supported intrinsics of ``_mm(256|512)_(mask(z))_loadrs_epi(8|16|32|64)``.
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- Support ISA of ``AMX-FP8``.
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Arm and AArch64 Support
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^^^^^^^^^^^^^^^^^^^^^^^

‎clang/include/clang/Basic/BuiltinsX86_64.def

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@@ -155,6 +155,12 @@ TARGET_BUILTIN(__builtin_ia32_cmpccxadd64, "SLLiv*SLLiSLLiIi", "n", "cmpccxadd")
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// AMX_FP16 FP16
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TARGET_BUILTIN(__builtin_ia32_tdpfp16ps, "vIUcIUcIUc", "n", "amx-fp16")
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// AMX FP8
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TARGET_BUILTIN(__builtin_ia32_tdpbf8ps, "vIUcUIcUIc", "n", "amx-fp8")
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TARGET_BUILTIN(__builtin_ia32_tdpbhf8ps, "vIUcUIcUIc", "n", "amx-fp8")
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TARGET_BUILTIN(__builtin_ia32_tdphbf8ps, "vIUcUIcUIc", "n", "amx-fp8")
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TARGET_BUILTIN(__builtin_ia32_tdphf8ps, "vIUcUIcUIc", "n", "amx-fp8")
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// RAO-INT
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TARGET_BUILTIN(__builtin_ia32_aadd64, "vv*SOi", "n", "raoint")
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TARGET_BUILTIN(__builtin_ia32_aand64, "vv*SOi", "n", "raoint")

‎clang/include/clang/Driver/Options.td

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@@ -6300,6 +6300,8 @@ def mamx_fp16 : Flag<["-"], "mamx-fp16">, Group<m_x86_Features_Group>;
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def mno_amx_fp16 : Flag<["-"], "mno-amx-fp16">, Group<m_x86_Features_Group>;
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def mamx_int8 : Flag<["-"], "mamx-int8">, Group<m_x86_Features_Group>;
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def mno_amx_int8 : Flag<["-"], "mno-amx-int8">, Group<m_x86_Features_Group>;
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def mamx_fp8 : Flag<["-"], "mamx-fp8">, Group<m_x86_Features_Group>;
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def mno_amx_fp8 : Flag<["-"], "mno-amx-fp8">, Group<m_x86_Features_Group>;
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def mamx_tile : Flag<["-"], "mamx-tile">, Group<m_x86_Features_Group>;
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def mno_amx_tile : Flag<["-"], "mno-amx-tile">, Group<m_x86_Features_Group>;
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def mcmpccxadd : Flag<["-"], "mcmpccxadd">, Group<m_x86_Features_Group>;

‎clang/lib/Basic/Targets/X86.cpp

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@@ -428,6 +428,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
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HasAMXTILE = true;
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} else if (Feature == "+amx-complex") {
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HasAMXCOMPLEX = true;
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} else if (Feature == "+amx-fp8") {
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HasAMXFP8 = true;
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} else if (Feature == "+cmpccxadd") {
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HasCMPCCXADD = true;
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} else if (Feature == "+raoint") {
@@ -947,6 +949,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
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Builder.defineMacro("__AMX_FP16__");
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if (HasAMXCOMPLEX)
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Builder.defineMacro("__AMX_COMPLEX__");
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if (HasAMXFP8)
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Builder.defineMacro("__AMX_FP8__");
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if (HasCMPCCXADD)
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Builder.defineMacro("__CMPCCXADD__");
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if (HasRAOINT)
@@ -1077,6 +1081,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
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.Case("amx-fp16", true)
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.Case("amx-int8", true)
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.Case("amx-tile", true)
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.Case("amx-fp8", true)
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.Case("avx", true)
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.Case("avx10.1-256", true)
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.Case("avx10.1-512", true)
@@ -1195,6 +1200,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
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.Case("amx-fp16", HasAMXFP16)
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.Case("amx-int8", HasAMXINT8)
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.Case("amx-tile", HasAMXTILE)
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.Case("amx-fp8", HasAMXFP8)
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.Case("avx", SSELevel >= AVX)
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.Case("avx10.1-256", HasAVX10_1)
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.Case("avx10.1-512", HasAVX10_1_512)

‎clang/lib/Basic/Targets/X86.h

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@@ -157,6 +157,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
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bool HasAMXINT8 = false;
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bool HasAMXBF16 = false;
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bool HasAMXCOMPLEX = false;
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bool HasAMXFP8 = false;
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bool HasSERIALIZE = false;
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bool HasTSXLDTRK = false;
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bool HasUSERMSR = false;

‎clang/lib/Headers/CMakeLists.txt

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@@ -149,6 +149,7 @@ set(x86_files
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amxcomplexintrin.h
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amxfp16intrin.h
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amxintrin.h
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amxfp8intrin.h
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avx10_2_512bf16intrin.h
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avx10_2_512convertintrin.h
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avx10_2_512minmaxintrin.h

‎clang/lib/Headers/amxfp8intrin.h

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@@ -0,0 +1,95 @@
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/*===------------- amxfp8intrin.h - AMX intrinsics -*- C++ -*----------------===
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*
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* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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* See https://llvm.org/LICENSE.txt for license information.
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* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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*
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*===------------------------------------------------------------------------===
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*/
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#ifndef __IMMINTRIN_H
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#error "Never use <amxfp8intrin.h> directly; include <immintrin.h> instead."
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#endif /* __IMMINTRIN_H */
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#ifndef __AMXFP8INTRIN_H
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#define __AMXFP8INTRIN_H
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#ifdef __x86_64__
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/// Peform the dot product of a BF8 value \a a by a BF8 value \a b accumulating
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/// into a Single Precision (FP32) source/dest \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// void _tile_dpbf8ps (__tile dst, __tile a, __tile b)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c TDPBF8PS instruction.
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///
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/// \param dst
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/// The destination tile. Max size is 1024 Bytes.
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/// \param a
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/// The 1st source tile. Max size is 1024 Bytes.
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/// \param b
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/// The 2nd source tile. Max size is 1024 Bytes.
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#define _tile_dpbf8ps(dst, a, b) __builtin_ia32_tdpbf8ps((dst), (a), (b))
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/// Perform the dot product of a BF8 value \a a by an HF8 value \a b
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/// accumulating into a Single Precision (FP32) source/dest \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// void _tile_dpbhf8ps (__tile dst, __tile a, __tile b)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c TDPBHF8PS instruction.
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///
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/// \param dst
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/// The destination tile. Max size is 1024 Bytes.
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/// \param a
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/// The 1st source tile. Max size is 1024 Bytes.
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/// \param b
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/// The 2nd source tile. Max size is 1024 Bytes.
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#define _tile_dpbhf8ps(dst, a, b) __builtin_ia32_tdpbhf8ps((dst), (a), (b))
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/// Perform the dot product of an HF8 value \a a by a BF8 value \a b
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/// accumulating into a Single Precision (FP32) source/dest \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// void _tile_dphbf8ps (__tile dst, __tile a, __tile b)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c TDPHBF8PS instruction.
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///
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/// \param dst
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/// The destination tile. Max size is 1024 Bytes.
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/// \param a
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/// The 1st source tile. Max size is 1024 Bytes.
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/// \param b
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/// The 2nd source tile. Max size is 1024 Bytes.
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#define _tile_dphbf8ps(dst, a, b) __builtin_ia32_tdphbf8ps((dst), (a), (b))
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/// Perform the dot product of an HF8 value \a a by an HF8 value \a b
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/// accumulating into a Single Precision (FP32) source/dest \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// void _tile_dphf8ps (__tile dst, __tile a, __tile b)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c TDPHF8PS instruction.
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///
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/// \param dst
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/// The destination tile. Max size is 1024 Bytes.
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/// \param a
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/// The 1st source tile. Max size is 1024 Bytes.
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/// \param b
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/// The 2nd source tile. Max size is 1024 Bytes.
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#define _tile_dphf8ps(dst, a, b) __builtin_ia32_tdphf8ps((dst), (a), (b))
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#endif /* __x86_64__ */
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#endif /* __AMXFP8INTRIN_H */

‎clang/lib/Headers/immintrin.h

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@@ -648,6 +648,10 @@ _storebe_i64(void * __P, long long __D) {
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#include <amxcomplexintrin.h>
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#endif
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#if !defined(__SCE__) || __has_feature(modules) || defined(__AMX_FP8__)
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#include <amxfp8intrin.h>
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#endif
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#if !defined(__SCE__) || __has_feature(modules) || \
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defined(__AVX512VP2INTERSECT__)
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#include <avx512vp2intersectintrin.h>

‎clang/lib/Sema/SemaX86.cpp

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@@ -640,6 +640,10 @@ bool SemaX86::CheckBuiltinTileArguments(unsigned BuiltinID, CallExpr *TheCall) {
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case X86::BI__builtin_ia32_tdpfp16ps:
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case X86::BI__builtin_ia32_tcmmimfp16ps:
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case X86::BI__builtin_ia32_tcmmrlfp16ps:
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case X86::BI__builtin_ia32_tdpbf8ps:
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case X86::BI__builtin_ia32_tdpbhf8ps:
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case X86::BI__builtin_ia32_tdphbf8ps:
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case X86::BI__builtin_ia32_tdphf8ps:
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return CheckBuiltinTileRangeAndDuplicate(TheCall, {0, 1, 2});
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}
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}

‎clang/test/CodeGen/X86/amx_fp8.c

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@@ -0,0 +1,27 @@
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// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +amx-fp8 \
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// RUN: -emit-llvm -o - -Werror -pedantic | FileCheck %s
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#include <immintrin.h>
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void test_amx(void *data) {
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//CHECK-LABEL: @test_amx
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//CHECK: call void @llvm.x86.tdpbf8ps(i8 1, i8 2, i8 3)
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_tile_dpbf8ps(1, 2, 3);
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}
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void test_amx2(void *data) {
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//CHECK-LABEL: @test_amx2
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//CHECK: call void @llvm.x86.tdpbhf8ps(i8 1, i8 2, i8 3)
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_tile_dpbhf8ps(1, 2, 3);
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}
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void test_amx3(void *data) {
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//CHECK-LABEL: @test_amx3
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//CHECK: call void @llvm.x86.tdphbf8ps(i8 1, i8 2, i8 3)
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_tile_dphbf8ps(1, 2, 3);
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}
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void test_amx4(void *data) {
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//CHECK-LABEL: @test_amx4
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//CHECK: call void @llvm.x86.tdphf8ps(i8 1, i8 2, i8 3)
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_tile_dphf8ps(1, 2, 3);
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}

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