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[RISCV] Add Qualcomm uC Xqcilia (Large Immediate Arithmetic) extension
This extension adds eight 48 bit large arithmetic instructions. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. Change-Id: Id7712ee41128ba11a3752cb4c2450a9c7be8e7d7
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‎clang/test/Driver/print-supported-extensions-riscv.c‎

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@@ -197,6 +197,7 @@
197197
// CHECK-NEXT: xqcics 0.2 'Xqcics' (Qualcomm uC Conditional Select Extension)
198198
// CHECK-NEXT: xqcicsr 0.2 'Xqcicsr' (Qualcomm uC CSR Extension)
199199
// CHECK-NEXT: xqciint 0.2 'Xqciint' (Qualcomm uC Interrupts Extension)
200+
// CHECK-NEXT: xqcilia 0.2 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
200201
// CHECK-NEXT: xqcilo 0.2 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
201202
// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
202203
// CHECK-NEXT: xqcisls 0.2 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)

‎llvm/docs/RISCVUsage.rst‎

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@@ -450,6 +450,9 @@ The current vendor extensions supported are:
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``experimental-Xqciint``
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LLVM implements `version 0.2 of the Qualcomm uC Interrupts extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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453+
``experimental-Xqcilia``
454+
LLVM implements `version 0.2 of the Qualcomm uC Large Immediate Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
455+
453456
``experimental-Xqcilo``
454457
LLVM implements `version 0.2 of the Qualcomm uC Large Offset Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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‎llvm/docs/ReleaseNotes.md‎

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@@ -296,6 +296,8 @@ Changes to the RISC-V Backend
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extension.
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* Adds experimental assembler support for the Qualcomm uC 'Xqcilo` (Large Offset Load Store)
298298
extension.
299+
* Adds experimental assembler support for the Qualcomm uC 'Xqcilia` (Large Immediate Arithmetic)
300+
extension.
299301
* Added ``Sdext`` and ``Sdtrig`` extensions.
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301303
Changes to the WebAssembly Backend

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -766,7 +766,9 @@ DecodeStatus RISCVDisassembler::getInstruction48(MCInst &MI, uint64_t &Size,
766766
TRY_TO_DECODE_FEATURE(
767767
RISCV::FeatureVendorXqcilo, DecoderTableXqcilo48,
768768
"Qualcomm uC Large Offset Load Store custom 48bit opcode table");
769-
769+
TRY_TO_DECODE_FEATURE(
770+
RISCV::FeatureVendorXqcilia, DecoderTableXqcilia48,
771+
"Qualcomm uC Large Immediate Arithmetic custom 48bit opcode table");
770772
return MCDisassembler::Fail;
771773
}
772774

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

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@@ -1310,6 +1310,14 @@ def HasVendorXqciint
13101310
AssemblerPredicate<(all_of FeatureVendorXqciint),
13111311
"'Xqciint' (Qualcomm uC Interrupts Extension)">;
13121312

1313+
def FeatureVendorXqcilia
1314+
: RISCVExperimentalExtension<0, 2, "Qualcomm uC Large Immediate Arithmetic Extension",
1315+
[FeatureStdExtZca]>;
1316+
def HasVendorXqcilia
1317+
: Predicate<"Subtarget->hasVendorXqcilia()">,
1318+
AssemblerPredicate<(all_of FeatureVendorXqcilia),
1319+
"'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)">;
1320+
13131321
def FeatureVendorXqcilo
13141322
: RISCVExperimentalExtension<0, 2, "Qualcomm uC Large Offset Load Store Extension",
13151323
[FeatureStdExtZca]>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

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@@ -245,6 +245,25 @@ class QCIRVInstESStore<bits<3> funct3, bits<2> funct2, string opcodestr>
245245
(ins GPRMem:$rs2, GPR:$rs1, simm26:$imm),
246246
opcodestr, "$rs2, ${imm}(${rs1})">;
247247

248+
class QCIRVInstEAI<bits<3> funct3, bits<1> funct1, string opcodestr>
249+
: RVInst48<(outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, imm32:$imm),
250+
opcodestr, "$rd, $imm", [], InstFormatOther> {
251+
bits<5> rd;
252+
bits<32> imm;
253+
254+
let Constraints = "$rd = $rd_wb";
255+
let Inst{47-16} = imm{31-0};
256+
let Inst{15} = funct1;
257+
let Inst{14-12} = funct3;
258+
let Inst{11-7} = rd;
259+
let Inst{6-0} = 0b0011111;
260+
}
261+
262+
class QCIRVInstEI<bits<3> funct3, bits<2> funct2, string opcodestr>
263+
: QCIRVInstEIBase<funct3, funct2, (outs GPRNoX0:$rd),
264+
(ins GPRNoX0:$rs1, simm26:$imm), opcodestr,
265+
"$rd, $rs1, $imm">;
266+
248267
//===----------------------------------------------------------------------===//
249268
// Instructions
250269
//===----------------------------------------------------------------------===//
@@ -435,6 +454,20 @@ let Predicates = [HasVendorXqcilo, IsRV32], DecoderNamespace = "Xqcilo" in {
435454
def QC_E_SW : QCIRVInstESStore<0b110, 0b11, "qc.e.sw">;
436455
} // Predicates = [HasVendorXqcilo, IsRV32], DecoderNamespace = "Xqcilo"
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457+
let Predicates = [HasVendorXqcilia, IsRV32], DecoderNamespace = "Xqcilia" in {
458+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
459+
def QC_E_XORAI : QCIRVInstEAI<0b001, 0b0, "qc.e.xorai">;
460+
def QC_E_ORAI : QCIRVInstEAI<0b001, 0b1, "qc.e.orai" >;
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def QC_E_ADDAI : QCIRVInstEAI<0b010, 0b0, "qc.e.addai">;
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def QC_E_ANDAI : QCIRVInstEAI<0b010, 0b1, "qc.e.andai">;
463+
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def QC_E_XORI : QCIRVInstEI<0b011, 0b00, "qc.e.xori">;
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def QC_E_ORI : QCIRVInstEI<0b011, 0b01, "qc.e.ori" >;
466+
def QC_E_ADDI : QCIRVInstEI<0b011, 0b10, "qc.e.addi">;
467+
def QC_E_ANDI : QCIRVInstEI<0b011, 0b11, "qc.e.andi">;
468+
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
469+
} // Predicates = [HasVendorXqcilia, IsRV32], DecoderNamespace = "Xqcilia"
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//===----------------------------------------------------------------------===//
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// Aliases
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//===----------------------------------------------------------------------===//

‎llvm/lib/TargetParser/RISCVISAInfo.cpp‎

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@@ -743,7 +743,8 @@ Error RISCVISAInfo::checkDependency() {
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bool HasZcmt = Exts.count("zcmt") != 0;
744744
static constexpr StringLiteral XqciExts[] = {
745745
{"xqcia"}, {"xqciac"}, {"xqcicli"}, {"xqcicm"}, {"xqcics"},
746-
{"xqcicsr"}, {"xqciint"}, {"xqcilo"}, {"xqcilsm"}, {"xqcisls"}};
746+
{"xqcicsr"}, {"xqciint"}, {"xqcilia"}, {"xqcilo"}, {"xqcilsm"},
747+
{"xqcisls"}};
747748

748749
if (HasI && HasE)
749750
return getIncompatibleError("i", "e");

‎llvm/test/CodeGen/RISCV/attributes.ll‎

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@@ -88,6 +88,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics %s -o - | FileCheck --check-prefix=RV32XQCICS %s
8989
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicsr %s -o - | FileCheck --check-prefix=RV32XQCICSR %s
9090
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqciint %s -o - | FileCheck --check-prefix=RV32XQCIINT %s
91+
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilia %s -o - | FileCheck --check-prefix=RV32XQCILIA %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilo %s -o - | FileCheck --check-prefix=RV32XQCILO %s
9293
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilsm %s -o - | FileCheck --check-prefix=RV32XQCILSM %s
9394
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisls %s -o - | FileCheck --check-prefix=RV32XQCISLS %s
@@ -404,6 +405,7 @@
404405
; RV32XQCICS: .attribute 5, "rv32i2p1_xqcics0p2"
405406
; RV32XQCICSR: .attribute 5, "rv32i2p1_xqcicsr0p2"
406407
; RV32XQCIINT: .attribute 5, "rv32i2p1_zca1p0_xqciint0p2"
408+
; RV32XQCILIA: .attribute 5, "rv32i2p1_zca1p0_xqcilia0p2"
407409
; RV32XQCILO: .attribute 5, "rv32i2p1_zca1p0_xqcilo0p2"
408410
; RV32XQCILSM: .attribute 5, "rv32i2p1_xqcilsm0p2"
409411
; RV32XQCISLS: .attribute 5, "rv32i2p1_xqcisls0p2"

‎llvm/test/MC/RISCV/xqcilia-invalid.s‎

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# Xqcilia - Qualcomm uC Large Immediate Arithmetic extension
2+
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcilia < %s 2>&1 \
3+
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-IMM %s
4+
# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcilia < %s 2>&1 \
5+
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-EXT %s
6+
7+
# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction
8+
qc.e.addai 9, 33554432
9+
10+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
11+
qc.e.addai x9
12+
13+
# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 4294967295]
14+
qc.e.addai x9, 20485546494
15+
16+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
17+
qc.e.addai x9, 33554432
18+
19+
20+
# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
21+
qc.e.addi x10, 9, 554432
22+
23+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
24+
qc.e.addi x10, x9
25+
26+
# CHECK-IMM: :[[@LINE+1]]:20: error: immediate must be an integer in the range [-33554432, 33554431]
27+
qc.e.addi x10, x9, 335544312
28+
29+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
30+
qc.e.addi x10, x9, 554432
31+
32+
33+
# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction
34+
qc.e.andai 9, 33554432
35+
36+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
37+
qc.e.andai x9
38+
39+
# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 4294967295]
40+
qc.e.andai x9, 20494437494
41+
42+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
43+
qc.e.andai x9, 33554432
44+
45+
46+
# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
47+
qc.e.andi x10, 9, 554432
48+
49+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
50+
qc.e.andi x10, x9
51+
52+
# CHECK-IMM: :[[@LINE+1]]:20: error: immediate must be an integer in the range [-33554432, 33554431]
53+
qc.e.andi x10, x9, 335544312
54+
55+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
56+
qc.e.andi x10, x9, 554432
57+
58+
59+
# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction
60+
qc.e.orai 9, 33554432
61+
62+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
63+
qc.e.orai x9
64+
65+
# CHECK-IMM: :[[@LINE+1]]:15: error: immediate must be an integer in the range [-2147483648, 4294967295]
66+
qc.e.orai x9, 20494437494
67+
68+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
69+
qc.e.orai x9, 33554432
70+
71+
72+
# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction
73+
qc.e.ori x10, 9, 554432
74+
75+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
76+
qc.e.ori x10, x9
77+
78+
# CHECK-IMM: :[[@LINE+1]]:19: error: immediate must be an integer in the range [-33554432, 33554431]
79+
qc.e.ori x10, x9, 335544312
80+
81+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
82+
qc.e.ori x10, x9, 554432
83+
84+
85+
86+
# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction
87+
qc.e.xorai 9, 33554432
88+
89+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
90+
qc.e.xorai x9
91+
92+
# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 4294967295]
93+
qc.e.xorai x9, 20494437494
94+
95+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
96+
qc.e.xorai x9, 33554432
97+
98+
99+
# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
100+
qc.e.xori x10, 9, 554432
101+
102+
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
103+
qc.e.xori x10, x9
104+
105+
# CHECK-IMM: :[[@LINE+1]]:20: error: immediate must be an integer in the range [-33554432, 33554431]
106+
qc.e.xori x10, x9, 335544312
107+
108+
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
109+
qc.e.xori x10, x9, 554432

‎llvm/test/MC/RISCV/xqcilia-valid.s‎

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@@ -0,0 +1,82 @@
1+
# Xqcilia - Qualcomm uC Large Immediate Arithmetic extension
2+
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilia -riscv-no-aliases -show-encoding \
3+
# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
4+
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilia < %s \
5+
# RUN: | llvm-objdump --mattr=+experimental-xqcilia -M no-aliases --no-print-imm-hex -d - \
6+
# RUN: | FileCheck -check-prefix=CHECK-INST %s
7+
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilia -show-encoding \
8+
# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
9+
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilia < %s \
10+
# RUN: | llvm-objdump --mattr=+experimental-xqcilia --no-print-imm-hex -d - \
11+
# RUN: | FileCheck -check-prefix=CHECK-INST %s
12+
13+
# CHECK-INST: qc.e.addai s1, -1
14+
# CHECK-ENC: encoding: [0x9f,0x24,0xff,0xff,0xff,0xff]
15+
qc.e.addai x9, 4294967295
16+
17+
# CHECK-INST: qc.e.addai s1, -2147483648
18+
# CHECK-ENC: encoding: [0x9f,0x24,0x00,0x00,0x00,0x80]
19+
qc.e.addai x9, -2147483648
20+
21+
22+
# CHECK-INST: qc.e.addi a0, s1, -33554432
23+
# CHECK-ENC: encoding: [0x1f,0xb5,0x04,0x80,0x00,0x80]
24+
qc.e.addi x10, x9, -33554432
25+
26+
# CHECK-INST: qc.e.addi a0, s1, 33554431
27+
# CHECK-ENC: encoding: [0x1f,0xb5,0xf4,0xbf,0xff,0x7f]
28+
qc.e.addi x10, x9, 33554431
29+
30+
31+
# CHECK-INST: qc.e.andai s1, -1
32+
# CHECK-ENC: encoding: [0x9f,0xa4,0xff,0xff,0xff,0xff]
33+
qc.e.andai x9, 4294967295
34+
35+
# CHECK-INST: qc.e.andai s1, -2147483648
36+
# CHECK-ENC: encoding: [0x9f,0xa4,0x00,0x00,0x00,0x80]
37+
qc.e.andai x9, -2147483648
38+
39+
40+
# CHECK-INST: qc.e.andi a0, s1, -33554432
41+
# CHECK-ENC: encoding: [0x1f,0xb5,0x04,0xc0,0x00,0x80]
42+
qc.e.andi x10, x9, -33554432
43+
44+
# CHECK-INST: qc.e.andi a0, s1, 33554431
45+
# CHECK-ENC: encoding: [0x1f,0xb5,0xf4,0xff,0xff,0x7f]
46+
qc.e.andi x10, x9, 33554431
47+
48+
49+
# CHECK-INST: qc.e.orai s1, -1
50+
# CHECK-ENC: encoding: [0x9f,0x94,0xff,0xff,0xff,0xff]
51+
qc.e.orai x9, 4294967295
52+
53+
# CHECK-INST: qc.e.orai s1, -2147483648
54+
# CHECK-ENC: encoding: [0x9f,0x94,0x00,0x00,0x00,0x80]
55+
qc.e.orai x9, -2147483648
56+
57+
58+
# CHECK-INST: qc.e.ori a0, s1, -33554432
59+
# CHECK-ENC: encoding: [0x1f,0xb5,0x04,0x40,0x00,0x80]
60+
qc.e.ori x10, x9, -33554432
61+
62+
# CHECK-INST: qc.e.ori a0, s1, 33554431
63+
# CHECK-ENC: encoding: [0x1f,0xb5,0xf4,0x7f,0xff,0x7f]
64+
qc.e.ori x10, x9, 33554431
65+
66+
67+
# CHECK-INST: qc.e.xorai s1, -1
68+
# CHECK-ENC: encoding: [0x9f,0x14,0xff,0xff,0xff,0xff]
69+
qc.e.xorai x9, 4294967295
70+
71+
# CHECK-INST: qc.e.xorai s1, -2147483648
72+
# CHECK-ENC: encoding: [0x9f,0x14,0x00,0x00,0x00,0x80]
73+
qc.e.xorai x9, -2147483648
74+
75+
76+
# CHECK-INST: qc.e.xori a0, s1, -33554432
77+
# CHECK-ENC: encoding: [0x1f,0xb5,0x04,0x00,0x00,0x80]
78+
qc.e.xori x10, x9, -33554432
79+
80+
# CHECK-INST: qc.e.xori a0, s1, 33554431
81+
# CHECK-ENC: encoding: [0x1f,0xb5,0xf4,0x3f,0xff,0x7f]
82+
qc.e.xori x10, x9, 33554431

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