[RISCV] Assembler support for XRivosVizip

This implements assembler support for the XRivosVizip custom/vendor
extension from Rivos Inc. which is defined in:
https://github.com/rivosinc/rivos-custom-extensions
(See src/xrivosvizip.adoc)

Codegen support will follow in a separate change.

Author: preames

clang/test/Driver/print-supported-extensions-riscv.c

@@ -202,6 +202,7 @@
 // CHECK-NEXT:     xqcilo               0.2       'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
 // CHECK-NEXT:     xqcilsm              0.2       'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
 // CHECK-NEXT:     xqcisls              0.2       'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
+// CHECK-NEXT:     xrivosvizip          0.1       'XRivosVizip' (Rivos Vector Register Zips)
 // CHECK-EMPTY:
 // CHECK-NEXT: Supported Profiles
 // CHECK-NEXT:     rva20s64

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

@@ -721,6 +721,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
                         "Qualcomm uC Conditional Move custom opcode table");
   TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqciint, DecoderTableXqciint32,
                         "Qualcomm uC Interrupts custom opcode table");
+  TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXRivosVizip, DecoderTableXRivos32,
+                        "Rivos custom opcode table");
   TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
 
   return MCDisassembler::Fail;

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -1333,6 +1333,15 @@ def HasVendorXqcilo
       AssemblerPredicate<(all_of FeatureVendorXqcilo),
                          "'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)">;
 
+// Rivos Extension(s)
+
+def FeatureVendorXRivosVizip
+    :  RISCVExperimentalExtension<0, 1, "Rivos Vector Register Zips">;
+def HasVendorXRivosVizip
+    : Predicate<"Subtarget->hasVendorXRivosVizip()">,
+      AssemblerPredicate<(all_of FeatureVendorXRivosVizip),
+                         "'XRivosVizip' (Rivos Vector Register Zips)">;
+
 //===----------------------------------------------------------------------===//
 // LLVM specific features and extensions
 //===----------------------------------------------------------------------===//

llvm/lib/Target/RISCV/RISCVInstrInfo.td

@@ -2148,6 +2148,7 @@ include "RISCVInstrInfoXCV.td"
 include "RISCVInstrInfoXwch.td"
 include "RISCVInstrInfoXqci.td"
 include "RISCVInstrInfoXMips.td"
+include "RISCVInstrInfoXRivos.td"
 
 //===----------------------------------------------------------------------===//
 // Global ISel

llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td

@@ -0,0 +1,27 @@
+//===-- RISCVInstrInfoXRivos.td --------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the vendor extensions defined by Rivos Inc.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// XRivosVizip
+//===----------------------------------------------------------------------===//
+
+
+let Predicates = [HasVendorXRivosVizip], hasSideEffects = 0,
+  mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, DecoderNamespace = "XRivos",
+  Inst<6-0> = OPC_CUSTOM_2.Value in  {
+defm RV_VZIPEVEN_V : VALU_IV_V<"rv.vzipeven", 0b001100>;
+defm RV_VZIPODD_V : VALU_IV_V<"rv.vzipodd", 0b011100>;
+defm RV_VZIP2A_V : VALU_IV_V<"rv.vzip2a", 0b000100>;
+defm RV_VZIP2B_V : VALU_IV_V<"rv.vzip2b", 0b010100>;
+defm RV_VUNZIP2A_V : VALU_IV_V<"rv.vunzip2a", 0b001000>;
+defm RV_VUNZIP2B_V : VALU_IV_V<"rv.vunzip2b", 0b011000>;
+}

llvm/test/MC/RISCV/xrivosvizip-valid.s

@@ -0,0 +1,30 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xrivosvizip -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-xrivosvizip < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-xrivosvizip -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-xrivosvizip -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-xrivosvizip < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-xrivosvizip -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: rv.vzipeven.vv    v1, v2, v3
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x32]
+rv.vzipeven.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vzipodd.vv  v1, v2, v3
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x72]
+rv.vzipodd.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ:  rv.vzip2a.vv   v1, v2, v3
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x12]
+rv.vzip2a.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vzip2b.vv   v1, v2, v3
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x52]
+rv.vzip2b.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vunzip2a.vv v1, v2, v3
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x22]
+rv.vunzip2a.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vunzip2b.vv v1, v2, v3
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x62]
+rv.vunzip2b.vv v1, v2, v3
+

llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

@@ -1128,6 +1128,7 @@ Experimental extensions
     xqcilo               0.2
     xqcilsm              0.2
     xqcisls              0.2
+    xrivosvizip          0.1
 
 Supported Profiles
     rva20s64