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Change the mixed instruction from xor to sub and change interface name from xor to mix
1 parent 2b02cb2 commit 823bd2f

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11 files changed

+42
-38
lines changed

11 files changed

+42
-38
lines changed

llvm/include/llvm/CodeGen/TargetLowering.h

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2134,11 +2134,10 @@ class LLVM_ABI TargetLoweringBase {
21342134
/// getIRStackGuard returns nullptr.
21352135
virtual Value *getSDagStackGuard(const Module &M) const;
21362136

2137-
/// If this function returns true, stack protection checks should XOR the
2138-
/// frame pointer (or whichever pointer is used to address locals) into the
2137+
/// If this function returns true, stack protection checks should mix the
21392138
/// stack guard value before checking it. getIRStackGuard must return nullptr
21402139
/// if this returns true.
2141-
virtual bool useStackGuardXorFP() const { return false; }
2140+
virtual bool useStackGuardMixCookie() const { return false; }
21422141

21432142
/// If the target has a standard stack protection check function that
21442143
/// performs validation and error handling, returns the function. Otherwise,
@@ -5797,8 +5796,9 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
57975796
/// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
57985797
virtual bool useLoadStackGuardNode(const Module &M) const { return false; }
57995798

5800-
virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
5801-
const SDLoc &DL, bool FailureBB) const {
5799+
virtual SDValue emitStackGuardMixCookie(SelectionDAG &DAG, SDValue Val,
5800+
const SDLoc &DL,
5801+
bool FailureBB) const {
58025802
llvm_unreachable("not implemented for this target");
58035803
}
58045804

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3934,8 +3934,9 @@ bool IRTranslator::emitSPDescriptorParent(StackProtectorDescriptor &SPD,
39343934
MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile)
39353935
.getReg(0);
39363936

3937-
if (TLI->useStackGuardXorFP()) {
3938-
LLVM_DEBUG(dbgs() << "Stack protector xor'ing with FP not yet implemented");
3937+
if (TLI->useStackGuardMixCookie()) {
3938+
LLVM_DEBUG(
3939+
dbgs() << "Stack protector mix'ing the cookie not yet implemented");
39393940
return false;
39403941
}
39413942

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3128,8 +3128,8 @@ void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
31283128
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), Align,
31293129
MachineMemOperand::MOVolatile);
31303130

3131-
if (TLI.useStackGuardXorFP())
3132-
GuardVal = TLI.emitStackGuardXorFP(DAG, GuardVal, dl, false);
3131+
if (TLI.useStackGuardMixCookie())
3132+
GuardVal = TLI.emitStackGuardMixCookie(DAG, GuardVal, dl, false);
31333133

31343134
// If we're using function-based instrumentation, call the guard check
31353135
// function
@@ -3237,8 +3237,8 @@ void SelectionDAGBuilder::visitSPDescriptorFailure(
32373237
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), Align,
32383238
MachineMemOperand::MOVolatile);
32393239

3240-
if (TLI.useStackGuardXorFP())
3241-
GuardVal = TLI.emitStackGuardXorFP(DAG, GuardVal, dl, true);
3240+
if (TLI.useStackGuardMixCookie())
3241+
GuardVal = TLI.emitStackGuardMixCookie(DAG, GuardVal, dl, true);
32423242

32433243
// The target provides a guard check function to validate the guard value.
32443244
// Generate a call to that function with the content of the guard slot as
@@ -7380,8 +7380,8 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
73807380
MachinePointerInfo(Global, 0), Align,
73817381
MachineMemOperand::MOVolatile);
73827382
}
7383-
if (TLI.useStackGuardXorFP())
7384-
Res = TLI.emitStackGuardXorFP(DAG, Res, sdl, false);
7383+
if (TLI.useStackGuardMixCookie())
7384+
Res = TLI.emitStackGuardMixCookie(DAG, Res, sdl, false);
73857385
DAG.setRoot(Chain);
73867386
setValue(&I, Res);
73877387
return;

llvm/lib/CodeGen/StackProtector.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -577,7 +577,7 @@ bool InsertStackProtectors(const TargetMachine *TM, Function *F,
577577
// impossible to emit the check in IR, so the target *must* support stack
578578
// protection in SDAG.
579579
bool SupportsSelectionDAGSP =
580-
TLI->useStackGuardXorFP() ||
580+
TLI->useStackGuardMixCookie() ||
581581
(EnableSelectionDAGSP && !TM->Options.EnableFastISel);
582582
AllocaInst *AI = nullptr; // Place on stack that stores the stack guard.
583583
BasicBlock *FailBB = nullptr;

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -29096,18 +29096,19 @@ bool AArch64TargetLowering::useLoadStackGuardNode(const Module &M) const {
2909629096
return true;
2909729097
}
2909829098

29099-
bool AArch64TargetLowering::useStackGuardXorFP() const {
29099+
bool AArch64TargetLowering::useStackGuardMixCookie() const {
2910029100
// Currently only MSVC CRTs XOR the frame pointer into the stack guard value.
2910129101
return Subtarget->getTargetTriple().isOSMSVCRT() &&
2910229102
!getTargetMachine().Options.EnableGlobalISel;
2910329103
}
2910429104

29105-
SDValue AArch64TargetLowering::emitStackGuardXorFP(SelectionDAG &DAG,
29106-
SDValue Val, const SDLoc &DL,
29107-
bool FailureBB) const {
29105+
SDValue AArch64TargetLowering::emitStackGuardMixCookie(SelectionDAG &DAG,
29106+
SDValue Val,
29107+
const SDLoc &DL,
29108+
bool FailureBB) const {
2910829109
if (FailureBB) {
2910929110
return DAG.getNode(
29110-
ISD::XOR, DL, Val.getValueType(), Val,
29111+
ISD::ADD, DL, Val.getValueType(), Val,
2911129112
DAG.getCopyFromReg(DAG.getEntryNode(), DL,
2911229113
getStackPointerRegisterToSaveRestore(), MVT::i64));
2911329114
}

llvm/lib/Target/AArch64/AArch64ISelLowering.h

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -358,9 +358,10 @@ class AArch64TargetLowering : public TargetLowering {
358358
shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
359359

360360
bool useLoadStackGuardNode(const Module &M) const override;
361-
bool useStackGuardXorFP() const override;
362-
SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL,
363-
bool FailureBB) const override;
361+
bool useStackGuardMixCookie() const override;
362+
SDValue emitStackGuardMixCookie(SelectionDAG &DAG, SDValue Val,
363+
const SDLoc &DL,
364+
bool FailureBB) const override;
364365
TargetLoweringBase::LegalizeTypeAction
365366
getPreferredVectorAction(MVT VT) const override;
366367

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2316,9 +2316,9 @@ bool AArch64InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
23162316
!Subtarget.getTargetLowering()
23172317
->getTargetMachine()
23182318
.Options.EnableGlobalISel) {
2319-
BuildMI(MBB, MI, DL, get(AArch64::EORXrr), Reg)
2320-
.addReg(Reg, RegState::Kill)
2321-
.addReg(AArch64::SP);
2319+
BuildMI(MBB, MI, DL, get(AArch64::SUBXrr), Reg)
2320+
.addReg(AArch64::SP)
2321+
.addReg(Reg, RegState::Kill);
23222322
}
23232323

23242324
MBB.erase(MI);

llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2733,14 +2733,14 @@ bool X86TargetLowering::useLoadStackGuardNode(const Module &M) const {
27332733
return Subtarget.isTargetMachO() && Subtarget.is64Bit();
27342734
}
27352735

2736-
bool X86TargetLowering::useStackGuardXorFP() const {
2736+
bool X86TargetLowering::useStackGuardMixCookie() const {
27372737
// Currently only MSVC CRTs XOR the frame pointer into the stack guard value.
27382738
return Subtarget.getTargetTriple().isOSMSVCRT() && !Subtarget.isTargetMachO();
27392739
}
27402740

2741-
SDValue X86TargetLowering::emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
2742-
const SDLoc &DL,
2743-
bool FailureBB) const {
2741+
SDValue X86TargetLowering::emitStackGuardMixCookie(SelectionDAG &DAG,
2742+
SDValue Val, const SDLoc &DL,
2743+
bool FailureBB) const {
27442744
EVT PtrTy = getPointerTy(DAG.getDataLayout());
27452745
unsigned XorOp = Subtarget.is64Bit() ? X86::XOR64_FP : X86::XOR32_FP;
27462746
MachineSDNode *Node = DAG.getMachineNode(XorOp, DL, PtrTy, Val);

llvm/lib/Target/X86/X86ISelLowering.h

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1590,10 +1590,11 @@ namespace llvm {
15901590
Value *getIRStackGuard(IRBuilderBase &IRB) const override;
15911591

15921592
bool useLoadStackGuardNode(const Module &M) const override;
1593-
bool useStackGuardXorFP() const override;
1593+
bool useStackGuardMixCookie() const override;
15941594
void insertSSPDeclarations(Module &M) const override;
1595-
SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL,
1596-
bool FailureBB) const override;
1595+
SDValue emitStackGuardMixCookie(SelectionDAG &DAG, SDValue Val,
1596+
const SDLoc &DL,
1597+
bool FailureBB) const override;
15971598

15981599
/// Return true if the target stores SafeStack pointer at a fixed offset in
15991600
/// some non-standard address space, and populates the address space and

llvm/test/CodeGen/AArch64/mingw-refptr.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -89,14 +89,14 @@ define dso_local void @sspFunc() #0 {
8989
; CHECK-NEXT: add x0, sp, #7
9090
; CHECK-NEXT: ldr x8, [x8, :lo12:.refptr.__stack_chk_guard]
9191
; CHECK-NEXT: ldr x8, [x8]
92-
; CHECK-NEXT: eor x8, x8, sp
92+
; CHECK-NEXT: sub x8, sp, x8
9393
; CHECK-NEXT: str x8, [sp, #8]
9494
; CHECK-NEXT: bl ptrUser
9595
; CHECK-NEXT: adrp x8, .refptr.__stack_chk_guard
9696
; CHECK-NEXT: ldr x8, [x8, :lo12:.refptr.__stack_chk_guard]
9797
; CHECK-NEXT: ldr x9, [sp, #8]
9898
; CHECK-NEXT: ldr x8, [x8]
99-
; CHECK-NEXT: eor x8, x8, sp
99+
; CHECK-NEXT: sub x8, sp, x8
100100
; CHECK-NEXT: cmp x8, x9
101101
; CHECK-NEXT: b.ne .LBB6_2
102102
; CHECK-NEXT: // %bb.1: // %entry

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