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daniilavdeevdaniilavdeev
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[RISCV][NFC] refactor CFI emitting
1 parent 107a646 commit 825bc96

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2 files changed

+97
-100
lines changed

2 files changed

+97
-100
lines changed

‎llvm/lib/Target/RISCV/RISCVFrameLowering.cpp‎

Lines changed: 94 additions & 98 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,88 @@
2727

2828
using namespace llvm;
2929

30+
static unsigned getCaleeSavedRVVNumRegs(const Register &BaseReg) {
31+
return RISCV::VRRegClass.contains(BaseReg) ? 1
32+
: RISCV::VRM2RegClass.contains(BaseReg) ? 2
33+
: RISCV::VRM4RegClass.contains(BaseReg) ? 4
34+
: 8;
35+
}
36+
37+
static MCRegister getRVVBaseRegister(const RISCVRegisterInfo &TRI, const Register &Reg) {
38+
MCRegister BaseReg = TRI.getSubReg(Reg, RISCV::sub_vrm1_0);
39+
// If it's not a grouped vector register, it doesn't have subregister, so
40+
// the base register is just itself.
41+
if (BaseReg == RISCV::NoRegister)
42+
BaseReg = Reg;
43+
return BaseReg;
44+
}
45+
46+
namespace {
47+
48+
struct CFIRestoreRegisterEmitter {
49+
CFIRestoreRegisterEmitter(MachineFunction &, const RISCVSubtarget &) {};
50+
51+
void emit(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII, const DebugLoc &DL, const CalleeSavedInfo &CS) const {
52+
Register Reg = CS.getReg();
53+
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
54+
nullptr, RI.getDwarfRegNum(Reg, true)));
55+
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
56+
.addCFIIndex(CFIIndex)
57+
.setMIFlag(MachineInstr::FrameDestroy);
58+
}
59+
};
60+
61+
class CFIStoreRegisterEmitter {
62+
MachineFrameInfo &MFI;
63+
64+
public:
65+
CFIStoreRegisterEmitter(MachineFunction &MF, const RISCVSubtarget &) : MFI{MF.getFrameInfo()} {};
66+
67+
void emit(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII, const DebugLoc &DL, const CalleeSavedInfo &CS) const {
68+
int FrameIdx = CS.getFrameIdx();
69+
int64_t Offset = MFI.getObjectOffset(FrameIdx);
70+
Register Reg = CS.getReg();
71+
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
72+
nullptr, RI.getDwarfRegNum(Reg, true), Offset));
73+
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
74+
.addCFIIndex(CFIIndex)
75+
.setMIFlag(MachineInstr::FrameSetup);
76+
}
77+
};
78+
79+
class CFIRestoreRVVRegisterEmitter {
80+
const llvm::RISCVRegisterInfo *TRI;
81+
82+
public:
83+
CFIRestoreRVVRegisterEmitter(MachineFunction &, const RISCVSubtarget &STI) : TRI{STI.getRegisterInfo()} {};
84+
85+
void emit(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII, const DebugLoc &DL, const CalleeSavedInfo &CS) const {
86+
MCRegister BaseReg = getRVVBaseRegister(*TRI, CS.getReg());
87+
unsigned NumRegs = getCaleeSavedRVVNumRegs(CS.getReg());
88+
for (unsigned i = 0; i < NumRegs; ++i) {
89+
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
90+
nullptr, RI.getDwarfRegNum(BaseReg + i, true)));
91+
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
92+
.addCFIIndex(CFIIndex)
93+
.setMIFlag(MachineInstr::FrameDestroy);
94+
}
95+
}
96+
};
97+
98+
}
99+
100+
template <typename Emitter>
101+
void RISCVFrameLowering::emitCFIForCSI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const SmallVector<CalleeSavedInfo, 8> &CSI) const {
102+
MachineFunction *MF = MBB.getParent();
103+
const RISCVRegisterInfo *RI = STI.getRegisterInfo();
104+
const RISCVInstrInfo *TII = STI.getInstrInfo();
105+
DebugLoc DL = MBB.findDebugLoc(MBBI);
106+
107+
Emitter E{*MF, STI};
108+
for (const auto &CS : CSI)
109+
E.emit(*MF, MBB, MBBI, *RI, *TII, DL, CS);
110+
}
111+
30112
static Align getABIStackAlignment(RISCVABI::ABI ABI) {
31113
if (ABI == RISCVABI::ABI_ILP32E)
32114
return Align(4);
@@ -607,16 +689,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
607689
.addCFIIndex(CFIIndex)
608690
.setMIFlag(MachineInstr::FrameSetup);
609691

610-
for (const auto &Entry : getPushOrLibCallsSavedInfo(MF, CSI)) {
611-
int FrameIdx = Entry.getFrameIdx();
612-
int64_t Offset = MFI.getObjectOffset(FrameIdx);
613-
Register Reg = Entry.getReg();
614-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
615-
nullptr, RI->getDwarfRegNum(Reg, true), Offset));
616-
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
617-
.addCFIIndex(CFIIndex)
618-
.setMIFlag(MachineInstr::FrameSetup);
619-
}
692+
emitCFIForCSI<CFIStoreRegisterEmitter>(MBB, MBBI, getPushOrLibCallsSavedInfo(MF, CSI));
620693
}
621694

622695
// FIXME (note copied from Lanai): This appears to be overallocating. Needs
@@ -658,16 +731,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
658731
.addCFIIndex(CFIIndex)
659732
.setMIFlag(MachineInstr::FrameSetup);
660733

661-
for (const auto &Entry : getPushOrLibCallsSavedInfo(MF, CSI)) {
662-
int FrameIdx = Entry.getFrameIdx();
663-
int64_t Offset = MFI.getObjectOffset(FrameIdx);
664-
Register Reg = Entry.getReg();
665-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
666-
nullptr, RI->getDwarfRegNum(Reg, true), Offset));
667-
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
668-
.addCFIIndex(CFIIndex)
669-
.setMIFlag(MachineInstr::FrameSetup);
670-
}
734+
emitCFIForCSI<CFIStoreRegisterEmitter>(MBB, MBBI, getPushOrLibCallsSavedInfo(MF, CSI));
671735
}
672736

673737
if (StackSize != 0) {
@@ -694,20 +758,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
694758

695759
// Iterate over list of callee-saved registers and emit .cfi_offset
696760
// directives.
697-
for (const auto &Entry : getUnmanagedCSI(MF, CSI)) {
698-
int FrameIdx = Entry.getFrameIdx();
699-
if (FrameIdx >= 0 &&
700-
MFI.getStackID(FrameIdx) == TargetStackID::ScalableVector)
701-
continue;
702-
703-
int64_t Offset = MFI.getObjectOffset(FrameIdx);
704-
Register Reg = Entry.getReg();
705-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
706-
nullptr, RI->getDwarfRegNum(Reg, true), Offset));
707-
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
708-
.addCFIIndex(CFIIndex)
709-
.setMIFlag(MachineInstr::FrameSetup);
710-
}
761+
emitCFIForCSI<CFIStoreRegisterEmitter>(MBB, MBBI, getUnmanagedCSI(MF, CSI));
711762

712763
// Generate new FP.
713764
if (hasFP(MF)) {
@@ -895,7 +946,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
895946
.setMIFlag(MachineInstr::FrameDestroy);
896947
}
897948

898-
emitCalleeSavedRVVEpilogCFI(MBB, LastFrameDestroy);
949+
emitCFIForCSI<CFIRestoreRVVRegisterEmitter>(MBB, LastFrameDestroy, getRVVCalleeSavedInfo(MF, CSI));
899950
}
900951

901952
if (FirstSPAdjustAmount) {
@@ -960,14 +1011,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
9601011
}
9611012

9621013
// Recover callee-saved registers.
963-
for (const auto &Entry : getUnmanagedCSI(MF, CSI)) {
964-
Register Reg = Entry.getReg();
965-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
966-
nullptr, RI->getDwarfRegNum(Reg, true)));
967-
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
968-
.addCFIIndex(CFIIndex)
969-
.setMIFlag(MachineInstr::FrameDestroy);
970-
}
1014+
emitCFIForCSI<CFIRestoreRegisterEmitter>(MBB, MBBI, getUnmanagedCSI(MF, CSI));
9711015

9721016
bool ApplyPop = RVFI->isPushable(MF) && MBBI != MBB.end() &&
9731017
MBBI->getOpcode() == RISCV::CM_POP;
@@ -976,7 +1020,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
9761020
// space. Align the stack size down to a multiple of 16. This is needed for
9771021
// RVE.
9781022
// FIXME: Can we increase the stack size to a multiple of 16 instead?
979-
uint64_t Spimm = std::min(alignDown(StackSize, 16), (uint64_t)48);
1023+
uint64_t Spimm = std::min(alignDown(StackSize, 16), static_cast<uint64_t>(48));
9801024
MBBI->getOperand(1).setImm(Spimm);
9811025
StackSize -= Spimm;
9821026

@@ -988,15 +1032,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
9881032
if (NextI == MBB.end() || NextI->getOpcode() != RISCV::PseudoRET) {
9891033
++MBBI;
9901034

991-
for (const auto &Entry : getPushOrLibCallsSavedInfo(MF, CSI)) {
992-
Register Reg = Entry.getReg();
993-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
994-
nullptr, RI->getDwarfRegNum(Reg, true)));
995-
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
996-
.addCFIIndex(CFIIndex)
997-
.setMIFlag(MachineInstr::FrameDestroy);
998-
}
999-
1035+
emitCFIForCSI<CFIRestoreRegisterEmitter>(MBB, MBBI, getPushOrLibCallsSavedInfo(MF, CSI));
1036+
10001037
// Update CFA offset. After CM_POP SP should be equal to CFA, so CFA offset
10011038
// should be a zero.
10021039
unsigned CFIIndex =
@@ -1006,7 +1043,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
10061043
.setMIFlag(MachineInstr::FrameDestroy);
10071044
}
10081045
}
1009-
1046+
10101047
// Deallocate stack if StackSize isn't a zero yet
10111048
if (StackSize != 0)
10121049
deallocateStack(MF, MBB, MBBI, DL, StackSize, 0);
@@ -1696,22 +1733,6 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
16961733
return true;
16971734
}
16981735

1699-
static unsigned getCaleeSavedRVVNumRegs(const Register &BaseReg) {
1700-
return RISCV::VRRegClass.contains(BaseReg) ? 1
1701-
: RISCV::VRM2RegClass.contains(BaseReg) ? 2
1702-
: RISCV::VRM4RegClass.contains(BaseReg) ? 4
1703-
: 8;
1704-
}
1705-
1706-
static MCRegister getRVVBaseRegister(const RISCVRegisterInfo &TRI, const Register &Reg) {
1707-
MCRegister BaseReg = TRI.getSubReg(Reg, RISCV::sub_vrm1_0);
1708-
// If it's not a grouped vector register, it doesn't have subregister, so
1709-
// the base register is just itself.
1710-
if (BaseReg == RISCV::NoRegister)
1711-
BaseReg = Reg;
1712-
return BaseReg;
1713-
}
1714-
17151736
void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI(
17161737
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, bool HasFP) const {
17171738
MachineFunction *MF = MBB.getParent();
@@ -1737,39 +1758,14 @@ void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI(
17371758
for (auto &CS : RVVCSI) {
17381759
// Insert the spill to the stack frame.
17391760
int FI = CS.getFrameIdx();
1740-
if (FI >= 0 && MFI.getStackID(FI) == TargetStackID::ScalableVector) {
1741-
MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg());
1742-
unsigned NumRegs = getCaleeSavedRVVNumRegs(CS.getReg());
1743-
for (unsigned i = 0; i < NumRegs; ++i) {
1744-
unsigned CFIIndex = MF->addFrameInst(createDefCFAOffset(
1745-
TRI, BaseReg + i, -FixedSize, MFI.getObjectOffset(FI) / 8 + i));
1746-
BuildMI(MBB, MI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1747-
.addCFIIndex(CFIIndex)
1748-
.setMIFlag(MachineInstr::FrameSetup);
1749-
}
1750-
}
1751-
}
1752-
}
1753-
1754-
void RISCVFrameLowering::emitCalleeSavedRVVEpilogCFI(
1755-
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const {
1756-
MachineFunction *MF = MBB.getParent();
1757-
const MachineFrameInfo &MFI = MF->getFrameInfo();
1758-
const RISCVRegisterInfo *RI = STI.getRegisterInfo();
1759-
const TargetInstrInfo &TII = *STI.getInstrInfo();
1760-
const RISCVRegisterInfo &TRI = *STI.getRegisterInfo();
1761-
DebugLoc DL = MBB.findDebugLoc(MI);
1762-
1763-
const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, MFI.getCalleeSavedInfo());
1764-
for (auto &CS : RVVCSI) {
17651761
MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg());
17661762
unsigned NumRegs = getCaleeSavedRVVNumRegs(CS.getReg());
17671763
for (unsigned i = 0; i < NumRegs; ++i) {
1768-
unsigned CFIIndex = MF->addFrameInst(MCCFIInstruction::createRestore(
1769-
nullptr, RI->getDwarfRegNum(BaseReg + i, true)));
1764+
unsigned CFIIndex = MF->addFrameInst(createDefCFAOffset(
1765+
TRI, BaseReg + i, -FixedSize, MFI.getObjectOffset(FI) / 8 + i));
17701766
BuildMI(MBB, MI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
17711767
.addCFIIndex(CFIIndex)
1772-
.setMIFlag(MachineInstr::FrameDestroy);
1768+
.setMIFlag(MachineInstr::FrameSetup);
17731769
}
17741770
}
17751771
}

‎llvm/lib/Target/RISCV/RISCVFrameLowering.h‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -91,11 +91,12 @@ class RISCVFrameLowering : public TargetFrameLowering {
9191
void emitCalleeSavedRVVPrologCFI(MachineBasicBlock &MBB,
9292
MachineBasicBlock::iterator MI,
9393
bool HasFP) const;
94-
void emitCalleeSavedRVVEpilogCFI(MachineBasicBlock &MBB,
95-
MachineBasicBlock::iterator MI) const;
9694
void deallocateStack(MachineFunction &MF, MachineBasicBlock &MBB,
9795
MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
9896
uint64_t &StackSize, int64_t CFAOffset) const;
97+
template <typename Emitter>
98+
void emitCFIForCSI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
99+
const SmallVector<CalleeSavedInfo, 8> &CSI) const;
99100

100101
std::pair<int64_t, Align>
101102
assignRVVStackObjectOffsets(MachineFunction &MF) const;

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