@@ -292,10 +292,8 @@ getVectorLoweringShape(EVT VectorEVT, const NVPTXSubtarget &STI,
292292static void ComputePTXValueVTs (const TargetLowering &TLI, const DataLayout &DL,
293293 LLVMContext &Ctx, CallingConv::ID CallConv,
294294 Type *Ty, SmallVectorImpl<EVT> &ValueVTs,
295- SmallVectorImpl<uint64_t > * Offsets,
295+ SmallVectorImpl<uint64_t > & Offsets,
296296 uint64_t StartingOffset = 0 ) {
297- assert (Offsets && " Offsets must be non-null" );
298-
299297 SmallVector<EVT, 16 > TempVTs;
300298 SmallVector<uint64_t , 16 > TempOffsets;
301299 ComputeValueVTs (TLI, DL, Ty, TempVTs, &TempOffsets, StartingOffset);
@@ -322,7 +320,7 @@ static void ComputePTXValueVTs(const TargetLowering &TLI, const DataLayout &DL,
322320 // leave it for now.
323321 for (unsigned I : seq (NumRegs)) {
324322 ValueVTs.push_back (RegisterVT);
325- Offsets-> push_back (Off + I * RegisterVT.getStoreSize ());
323+ Offsets. push_back (Off + I * RegisterVT.getStoreSize ());
326324 }
327325 }
328326}
@@ -1563,7 +1561,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
15631561 } else {
15641562 SmallVector<EVT, 16 > VTs;
15651563 SmallVector<uint64_t , 16 > Offsets;
1566- ComputePTXValueVTs (*this , DL, Ctx, CLI.CallConv , Arg.Ty , VTs, & Offsets,
1564+ ComputePTXValueVTs (*this , DL, Ctx, CLI.CallConv , Arg.Ty , VTs, Offsets,
15671565 VAOffset);
15681566 assert (VTs.size () == Offsets.size () && " Size mismatch" );
15691567 assert (VTs.size () == ArgOuts.size () && " Size mismatch" );
@@ -1714,7 +1712,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
17141712 if (!Ins.empty ()) {
17151713 SmallVector<EVT, 16 > VTs;
17161714 SmallVector<uint64_t , 16 > Offsets;
1717- ComputePTXValueVTs (*this , DL, Ctx, CLI.CallConv , RetTy, VTs, & Offsets);
1715+ ComputePTXValueVTs (*this , DL, Ctx, CLI.CallConv , RetTy, VTs, Offsets);
17181716 assert (VTs.size () == Ins.size () && " Bad value decomposition" );
17191717
17201718 const Align RetAlign = getArgumentAlignment (CB, RetTy, 0 , DL);
@@ -3416,7 +3414,7 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
34163414 } else {
34173415 SmallVector<EVT, 16 > VTs;
34183416 SmallVector<uint64_t , 16 > Offsets;
3419- ComputePTXValueVTs (*this , DL, Ctx, CallConv, Ty, VTs, & Offsets, 0 );
3417+ ComputePTXValueVTs (*this , DL, Ctx, CallConv, Ty, VTs, Offsets);
34203418 assert (VTs.size () == ArgIns.size () && " Size mismatch" );
34213419 assert (VTs.size () == Offsets.size () && " Size mismatch" );
34223420
@@ -3486,7 +3484,7 @@ NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
34863484
34873485 SmallVector<EVT, 16 > VTs;
34883486 SmallVector<uint64_t , 16 > Offsets;
3489- ComputePTXValueVTs (*this , DL, Ctx, CallConv, RetTy, VTs, & Offsets);
3487+ ComputePTXValueVTs (*this , DL, Ctx, CallConv, RetTy, VTs, Offsets);
34903488 assert (VTs.size () == OutVals.size () && " Bad return value decomposition" );
34913489
34923490 const auto GetRetVal = [&](unsigned I) -> SDValue {
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