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Added smed3, umed3 amdgcn.& -> asm lits; Added rocdl -> llvm lowering lit
Signed-off-by: keshavvinayak01 <[email protected]>
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‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smed3.i16.ll‎

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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}test_smed3_i16:
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; GCN: v_med3_i16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @test_smed3_i16(ptr addrspace(1) %out, i32 %src0.arg, i32 %src1.arg, i32 %src2.arg) #1 {
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%src0.i16 = trunc i32 %src0.arg to i16
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%src1.i16 = trunc i32 %src1.arg to i16
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%src2.i16 = trunc i32 %src2.arg to i16
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%med3 = call i16 @llvm.amdgcn.smed3.i16(i16 %src0.i16, i16 %src1.i16, i16 %src2.i16)
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store i16 %med3, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_smed3_zero_i16:
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; GCN: v_med3_i16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, 0
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define amdgpu_kernel void @test_smed3_zero_i16(ptr addrspace(1) %out, i32 %src0.arg, i32 %src1.arg) #1 {
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%src0.i16 = trunc i32 %src0.arg to i16
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%src1.i16 = trunc i32 %src1.arg to i16
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%med3 = call i16 @llvm.amdgcn.smed3.i16(i16 %src0.i16, i16 %src1.i16, i16 0)
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store i16 %med3, ptr addrspace(1) %out
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ret void
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}
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declare i16 @llvm.amdgcn.smed3.i16(i16, i16, i16) #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smed3.ll‎

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; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}test_smed3:
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; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @test_smed3(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) #1 {
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%med3 = call i32 @llvm.amdgcn.smed3.i32(i32 %src0, i32 %src1, i32 %src2)
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store i32 %med3, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_smed3_multi_use:
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; GCN: v_med3_i32 [[MED3:v[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_mul_lo_i32 v{{[0-9]+}}, [[MED3]], s{{[0-9]+}}
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define amdgpu_kernel void @test_smed3_multi_use(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2, i32 %mul.arg) #1 {
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%med3 = call i32 @llvm.amdgcn.smed3.i32(i32 %src0, i32 %src1, i32 %src2)
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%med3.user = mul i32 %med3, %mul.arg
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store volatile i32 %med3.user, ptr addrspace(1) %out
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store volatile i32 %med3, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_smed3_constants:
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; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, 42
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define amdgpu_kernel void @test_smed3_constants(ptr addrspace(1) %out, i32 %src0, i32 %src1) #1 {
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%med3 = call i32 @llvm.amdgcn.smed3.i32(i32 %src0, i32 %src1, i32 42)
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store i32 %med3, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_smed3_zero:
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; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, 0
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define amdgpu_kernel void @test_smed3_zero(ptr addrspace(1) %out, i32 %src0, i32 %src1) #1 {
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%med3 = call i32 @llvm.amdgcn.smed3.i32(i32 %src0, i32 %src1, i32 0)
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store i32 %med3, ptr addrspace(1) %out
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ret void
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}
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declare i32 @llvm.amdgcn.smed3.i32(i32, i32, i32) #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.umed3.i16.ll‎

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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}test_umed3_i16:
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; GCN: v_med3_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @test_umed3_i16(ptr addrspace(1) %out, i32 %src0.arg, i32 %src1.arg, i32 %src2.arg) #1 {
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%src0.i16 = trunc i32 %src0.arg to i16
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%src1.i16 = trunc i32 %src1.arg to i16
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%src2.i16 = trunc i32 %src2.arg to i16
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%med3 = call i16 @llvm.amdgcn.umed3.i16(i16 %src0.i16, i16 %src1.i16, i16 %src2.i16)
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store i16 %med3, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_umed3_zero_i16:
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; GCN: v_med3_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, 0
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define amdgpu_kernel void @test_umed3_zero_i16(ptr addrspace(1) %out, i32 %src0.arg, i32 %src1.arg) #1 {
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%src0.i16 = trunc i32 %src0.arg to i16
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%src1.i16 = trunc i32 %src1.arg to i16
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%med3 = call i16 @llvm.amdgcn.umed3.i16(i16 %src0.i16, i16 %src1.i16, i16 0)
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store i16 %med3, ptr addrspace(1) %out
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ret void
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}
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declare i16 @llvm.amdgcn.umed3.i16(i16, i16, i16) #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.umed3.ll‎

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; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}test_umed3:
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; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @test_umed3(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) #1 {
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%med3 = call i32 @llvm.amdgcn.umed3.i32(i32 %src0, i32 %src1, i32 %src2)
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store i32 %med3, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_umed3_multi_use:
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; GCN: v_med3_u32 [[MED3:v[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_mul_lo_i32 v{{[0-9]+}}, [[MED3]], s{{[0-9]+}}
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define amdgpu_kernel void @test_umed3_multi_use(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2, i32 %mul.arg) #1 {
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%med3 = call i32 @llvm.amdgcn.umed3.i32(i32 %src0, i32 %src1, i32 %src2)
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%med3.user = mul i32 %med3, %mul.arg
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store volatile i32 %med3.user, ptr addrspace(1) %out
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store volatile i32 %med3, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_umed3_constants:
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; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, 42
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define amdgpu_kernel void @test_umed3_constants(ptr addrspace(1) %out, i32 %src0, i32 %src1) #1 {
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%med3 = call i32 @llvm.amdgcn.umed3.i32(i32 %src0, i32 %src1, i32 42)
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store i32 %med3, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_umed3_zero:
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; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, 0
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define amdgpu_kernel void @test_umed3_zero(ptr addrspace(1) %out, i32 %src0, i32 %src1) #1 {
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%med3 = call i32 @llvm.amdgcn.umed3.i32(i32 %src0, i32 %src1, i32 0)
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store i32 %med3, ptr addrspace(1) %out
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ret void
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}
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declare i32 @llvm.amdgcn.umed3.i32(i32, i32, i32) #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }

‎mlir/test/Target/LLVMIR/rocdl.mlir‎

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@@ -1298,6 +1298,48 @@ llvm.func @rocdl_last_use(%ptr: !llvm.ptr<1>) -> i32 {
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llvm.return %ret : i32
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}
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llvm.func @test_med3_f16(%arg0: f16, %arg1: f16, %arg2: f16) -> f16 {
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// CHECK-LABEL: define half @test_med3_f16(half %0, half %1, half %2)
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%0 = rocdl.med3.f16 %arg0, %arg1, %arg2 : (f16, f16, f16) -> f16
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llvm.return %0 : f16
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// CHECK: call half @llvm.amdgcn.fmed3.f16(half %0, half %1, half %2)
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}
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llvm.func @test_med3_f32(%arg0: f32, %arg1: f32, %arg2: f32) -> f32 {
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// CHECK-LABEL: define float @test_med3_f32(float %0, float %1, float %2)
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%0 = rocdl.med3.f32 %arg0, %arg1, %arg2 : (f32, f32, f32) -> f32
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llvm.return %0 : f32
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// CHECK: call float @llvm.amdgcn.fmed3.f32(float %0, float %1, float %2)
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}
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llvm.func @test_med3_i16(%arg0: i16, %arg1: i16, %arg2: i16) -> i16 {
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// CHECK-LABEL: define i16 @test_med3_i16(i16 %0, i16 %1, i16 %2)
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%0 = rocdl.med3.i16 %arg0, %arg1, %arg2 : (i16, i16, i16) -> i16
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llvm.return %0 : i16
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// CHECK: call i16 @llvm.amdgcn.smed3.i16(i16 %0, i16 %1, i16 %2)
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}
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llvm.func @test_med3_i32(%arg0: i32, %arg1: i32, %arg2: i32) -> i32 {
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// CHECK-LABEL: define i32 @test_med3_i32(i32 %0, i32 %1, i32 %2)
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%0 = rocdl.med3.i32 %arg0, %arg1, %arg2 : (i32, i32, i32) -> i32
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llvm.return %0 : i32
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// CHECK: call i32 @llvm.amdgcn.smed3.i32(i32 %0, i32 %1, i32 %2)
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}
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llvm.func @test_med3_u16(%arg0: i16, %arg1: i16, %arg2: i16) -> i16 {
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// CHECK-LABEL: define i16 @test_med3_u16(i16 %0, i16 %1, i16 %2)
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%0 = rocdl.med3.u16 %arg0, %arg1, %arg2 : (i16, i16, i16) -> i16
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llvm.return %0 : i16
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// CHECK: call i16 @llvm.amdgcn.umed3.i16(i16 %0, i16 %1, i16 %2)
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}
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llvm.func @test_med3_u32(%arg0: i32, %arg1: i32, %arg2: i32) -> i32 {
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// CHECK-LABEL: define i32 @test_med3_u32(i32 %0, i32 %1, i32 %2)
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%0 = rocdl.med3.u32 %arg0, %arg1, %arg2 : (i32, i32, i32) -> i32
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llvm.return %0 : i32
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// CHECK: call i32 @llvm.amdgcn.umed3.i32(i32 %0, i32 %1, i32 %2)
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}
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// CHECK-DAG: attributes #[[$KERNEL_ATTRS]] = { "amdgpu-flat-work-group-size"="1,256" "uniform-work-group-size"="true" }
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// CHECK-DAG: attributes #[[$KERNEL_WORKGROUP_ATTRS]] = { "amdgpu-flat-work-group-size"="1,1024"
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// CHECK-DAG: attributes #[[$KNOWN_BLOCK_SIZE_ATTRS]] = { "amdgpu-flat-work-group-size"="128,128"

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