@@ -23,7 +23,7 @@ using namespace mlir::vector;
2323
2424namespace {
2525
26- // / Lowers a `vector.shuffle` operation with mix -size inputs to a new
26+ // / Lowers a `vector.shuffle` operation with mixed -size inputs to a new
2727// / `vector.shuffle` which promotes the smaller input to the larger vector size
2828// / and an updated version of the original `vector.shuffle`.
2929// /
@@ -33,12 +33,16 @@ namespace {
3333// /
3434// / is lowered to:
3535// /
36- // / %0 = vector.shuffle %v1, %v1 [0, 1, -1, -1] :
37- // / vector<2xf32>, vector<2xf32>
38- // / %1 = vector.shuffle %0, %v2 [0, 4, 1, 5] :
36+ // / %0 = vector.shuffle %v1, %v1 [0, 1, -1, -1] :
37+ // / vector<2xf32>, vector<2xf32>
38+ // / %1 = vector.shuffle %0, %v2 [0, 4, 1, 5] :
3939// / vector<4xf32>, vector<4xf32>
4040// /
41- struct MixSizeInputShuffleOpRewrite final
41+ // / Note: This transformation helps legalize vector.shuffle ops when lowering
42+ // / to SPIR-V/LLVM, which don't support shuffle operations with mixed-size
43+ // / inputs.
44+ // /
45+ struct MixedSizeInputShuffleOpRewrite final
4246 : OpRewritePattern<vector::ShuffleOp> {
4347 using OpRewritePattern::OpRewritePattern;
4448
@@ -51,7 +55,7 @@ struct MixSizeInputShuffleOpRewrite final
5155 if (v1Type.getRank () != 1 || v2Type.getRank () != 1 )
5256 return failure ();
5357
54- // Bail out if inputs don't have mixed sized .
58+ // Bail out if inputs don't have mixed sizes .
5559 int64_t v1OrigNumElems = v1Type.getNumElements ();
5660 int64_t v2OrigNumElems = v2Type.getNumElements ();
5761 if (v1OrigNumElems == v2OrigNumElems)
@@ -102,5 +106,5 @@ struct MixSizeInputShuffleOpRewrite final
102106
103107void mlir::vector::populateVectorShuffleLoweringPatterns (
104108 RewritePatternSet &patterns, PatternBenefit benefit) {
105- patterns.add <MixSizeInputShuffleOpRewrite >(patterns.getContext (), benefit);
109+ patterns.add <MixedSizeInputShuffleOpRewrite >(patterns.getContext (), benefit);
106110}
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