[RISCV] Don't commute with shift if XAndesPerf is enabled.

Generate the code for nds.lea.{h,w,d} similiar to sh{1,2,3}add

Author: tclin914

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -20413,8 +20413,8 @@ bool RISCVTargetLowering::isDesirableToCommuteWithShift(
     auto *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1));
 
     // Bail if we might break a sh{1,2,3}add pattern.
-    if (Subtarget.hasStdExtZba() && C2 && C2->getZExtValue() >= 1 &&
-        C2->getZExtValue() <= 3 && N->hasOneUse() &&
+    if ((Subtarget.hasStdExtZba() || Subtarget.hasVendorXAndesPerf()) && C2 &&
+        C2->getZExtValue() >= 1 && C2->getZExtValue() <= 3 && N->hasOneUse() &&
         N->user_begin()->getOpcode() == ISD::ADD &&
         !isUsedByLdSt(*N->user_begin(), nullptr) &&
         !isa<ConstantSDNode>(N->user_begin()->getOperand(1)))

llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll

@@ -356,10 +356,8 @@ define i64 @add_shl_moreOneUse_sh1add(i64 %x) {
 ;
 ; XANDESPERF-LABEL: add_shl_moreOneUse_sh1add:
 ; XANDESPERF:       # %bb.0:
-; XANDESPERF-NEXT:    ori a1, a0, 1
-; XANDESPERF-NEXT:    slli a0, a0, 1
-; XANDESPERF-NEXT:    ori a0, a0, 2
-; XANDESPERF-NEXT:    add a0, a0, a1
+; XANDESPERF-NEXT:    ori a0, a0, 1
+; XANDESPERF-NEXT:    nds.lea.h a0, a0, a0
 ; XANDESPERF-NEXT:    ret
   %or = or i64 %x, 1
   %mul = shl i64 %or, 1
@@ -384,10 +382,8 @@ define i64 @add_shl_moreOneUse_sh2add(i64 %x) {
 ;
 ; XANDESPERF-LABEL: add_shl_moreOneUse_sh2add:
 ; XANDESPERF:       # %bb.0:
-; XANDESPERF-NEXT:    ori a1, a0, 1
-; XANDESPERF-NEXT:    slli a0, a0, 2
-; XANDESPERF-NEXT:    ori a0, a0, 4
-; XANDESPERF-NEXT:    add a0, a0, a1
+; XANDESPERF-NEXT:    ori a0, a0, 1
+; XANDESPERF-NEXT:    nds.lea.w a0, a0, a0
 ; XANDESPERF-NEXT:    ret
   %or = or i64 %x, 1
   %mul = shl i64 %or, 2
@@ -412,10 +408,8 @@ define i64 @add_shl_moreOneUse_sh3add(i64 %x) {
 ;
 ; XANDESPERF-LABEL: add_shl_moreOneUse_sh3add:
 ; XANDESPERF:       # %bb.0:
-; XANDESPERF-NEXT:    ori a1, a0, 1
-; XANDESPERF-NEXT:    slli a0, a0, 3
-; XANDESPERF-NEXT:    ori a0, a0, 8
-; XANDESPERF-NEXT:    add a0, a0, a1
+; XANDESPERF-NEXT:    ori a0, a0, 1
+; XANDESPERF-NEXT:    nds.lea.d a0, a0, a0
 ; XANDESPERF-NEXT:    ret
   %or = or i64 %x, 1
   %mul = shl i64 %or, 3

llvm/test/CodeGen/RISCV/add_shl_constant.ll

@@ -19,8 +19,8 @@ define i32 @add_shl_oneUse(i32 %x, i32 %y) nounwind {
 ;
 ; XANDESPERF-LABEL: add_shl_oneUse:
 ; XANDESPERF:       # %bb.0:
+; XANDESPERF-NEXT:    addi a0, a0, 123
 ; XANDESPERF-NEXT:    nds.lea.d a0, a1, a0
-; XANDESPERF-NEXT:    addi a0, a0, 984
 ; XANDESPERF-NEXT:    ret
   %add.0 = add i32 %x, 123
   %shl = shl i32 %add.0, 3
@@ -257,10 +257,8 @@ define i32 @add_shl_moreOneUse_sh1add(i32 %x) {
 ;
 ; XANDESPERF-LABEL: add_shl_moreOneUse_sh1add:
 ; XANDESPERF:       # %bb.0:
-; XANDESPERF-NEXT:    ori a1, a0, 1
-; XANDESPERF-NEXT:    slli a0, a0, 1
-; XANDESPERF-NEXT:    ori a0, a0, 2
-; XANDESPERF-NEXT:    add a0, a0, a1
+; XANDESPERF-NEXT:    ori a0, a0, 1
+; XANDESPERF-NEXT:    nds.lea.h a0, a0, a0
 ; XANDESPERF-NEXT:    ret
   %or = or i32 %x, 1
   %mul = shl i32 %or, 1
@@ -285,10 +283,8 @@ define i32 @add_shl_moreOneUse_sh2add(i32 %x) {
 ;
 ; XANDESPERF-LABEL: add_shl_moreOneUse_sh2add:
 ; XANDESPERF:       # %bb.0:
-; XANDESPERF-NEXT:    ori a1, a0, 1
-; XANDESPERF-NEXT:    slli a0, a0, 2
-; XANDESPERF-NEXT:    ori a0, a0, 4
-; XANDESPERF-NEXT:    add a0, a0, a1
+; XANDESPERF-NEXT:    ori a0, a0, 1
+; XANDESPERF-NEXT:    nds.lea.w a0, a0, a0
 ; XANDESPERF-NEXT:    ret
   %or = or i32 %x, 1
   %mul = shl i32 %or, 2
@@ -313,10 +309,8 @@ define i32 @add_shl_moreOneUse_sh3add(i32 %x) {
 ;
 ; XANDESPERF-LABEL: add_shl_moreOneUse_sh3add:
 ; XANDESPERF:       # %bb.0:
-; XANDESPERF-NEXT:    ori a1, a0, 1
-; XANDESPERF-NEXT:    slli a0, a0, 3
-; XANDESPERF-NEXT:    ori a0, a0, 8
-; XANDESPERF-NEXT:    add a0, a0, a1
+; XANDESPERF-NEXT:    ori a0, a0, 1
+; XANDESPERF-NEXT:    nds.lea.d a0, a0, a0
 ; XANDESPERF-NEXT:    ret
   %or = or i32 %x, 1
   %mul = shl i32 %or, 3