[RISCV][Docs] Add bfloat types to RISCVVectorExtension.rst. NFC (#147867)

Author: topperc

llvm/docs/RISCV/RISCVVectorExtension.rst

@@ -19,23 +19,25 @@ On RISC-V ``n`` and ``ty`` control LMUL and SEW respectively.
 LLVM only supports ELEN=32 or ELEN=64, so ``vscale`` is defined as VLEN/64 (see ``RISCV::RVVBitsPerBlock``).
 Note this means that VLEN must be at least 64, so VLEN=32 isn't currently supported.
 
-+-------------------+---------------+----------------+------------------+-------------------+-------------------+-------------------+-------------------+
-|                   | LMUL=⅛        | LMUL=¼         | LMUL=½           | LMUL=1            | LMUL=2            | LMUL=4            | LMUL=8            |
-+===================+===============+================+==================+===================+===================+===================+===================+
-| i64 (ELEN=64)     | N/A           | N/A            | N/A              | <v x 1 x i64>     | <v x 2 x i64>     | <v x 4 x i64>     | <v x 8 x i64>     |
-+-------------------+---------------+----------------+------------------+-------------------+-------------------+-------------------+-------------------+
-| i32               | N/A           | N/A            | <v x 1 x i32>    | <v x 2 x i32>     | <v x 4 x i32>     | <v x 8 x i32>     | <v x 16 x i32>    |
-+-------------------+---------------+----------------+------------------+-------------------+-------------------+-------------------+-------------------+
-| i16               | N/A           | <v x 1 x i16>  | <v x 2 x i16>    | <v x 4 x i16>     | <v x 8 x i16>     | <v x 16 x i16>    | <v x 32 x i16>    |
-+-------------------+---------------+----------------+------------------+-------------------+-------------------+-------------------+-------------------+
-| i8                | <v x 1 x i8>  | <v x 2 x i8>   | <v x 4 x i8>     | <v x 8 x i8>      | <v x 16 x i8>     | <v x 32 x i8>     | <v x 64 x i8>     |
-+-------------------+---------------+----------------+------------------+-------------------+-------------------+-------------------+-------------------+
-| double (ELEN=64)  | N/A           | N/A            | N/A              | <v x 1 x double>  | <v x 2 x double>  | <v x 4 x double>  | <v x 8 x double>  |
-+-------------------+---------------+----------------+------------------+-------------------+-------------------+-------------------+-------------------+
-| float             | N/A           | N/A            | <v x 1 x float>  | <v x 2 x float>   | <v x 4 x float>   | <v x 8 x float>   | <v x 16 x float>  |
-+-------------------+---------------+----------------+------------------+-------------------+-------------------+-------------------+-------------------+
-| half              | N/A           | <v x 1 x half> | <v x 2 x half>   | <v x 4 x half>    | <v x 8 x half>    | <v x 16 x half>   | <v x 32 x half>   |
-+-------------------+---------------+----------------+------------------+-------------------+-------------------+-------------------+-------------------+
++-------------------+---------------+------------------+------------------+-------------------+-------------------+-------------------+-------------------+
+|                   | LMUL=⅛        | LMUL=¼           | LMUL=½           | LMUL=1            | LMUL=2            | LMUL=4            | LMUL=8            |
++===================+===============+==================+==================+===================+===================+===================+===================+
+| i64 (ELEN=64)     | N/A           | N/A              | N/A              | <v x 1 x i64>     | <v x 2 x i64>     | <v x 4 x i64>     | <v x 8 x i64>     |
++-------------------+---------------+------------------+------------------+-------------------+-------------------+-------------------+-------------------+
+| i32               | N/A           | N/A              | <v x 1 x i32>    | <v x 2 x i32>     | <v x 4 x i32>     | <v x 8 x i32>     | <v x 16 x i32>    |
++-------------------+---------------+------------------+------------------+-------------------+-------------------+-------------------+-------------------+
+| i16               | N/A           | <v x 1 x i16>    | <v x 2 x i16>    | <v x 4 x i16>     | <v x 8 x i16>     | <v x 16 x i16>    | <v x 32 x i16>    |
++-------------------+---------------+------------------+------------------+-------------------+-------------------+-------------------+-------------------+
+| i8                | <v x 1 x i8>  | <v x 2 x i8>     | <v x 4 x i8>     | <v x 8 x i8>      | <v x 16 x i8>     | <v x 32 x i8>     | <v x 64 x i8>     |
++-------------------+---------------+------------------+------------------+-------------------+-------------------+-------------------+-------------------+
+| double (ELEN=64)  | N/A           | N/A              | N/A              | <v x 1 x double>  | <v x 2 x double>  | <v x 4 x double>  | <v x 8 x double>  |
++-------------------+---------------+------------------+------------------+-------------------+-------------------+-------------------+-------------------+
+| float             | N/A           | N/A              | <v x 1 x float>  | <v x 2 x float>   | <v x 4 x float>   | <v x 8 x float>   | <v x 16 x float>  |
++-------------------+---------------+------------------+------------------+-------------------+-------------------+-------------------+-------------------+
+| half              | N/A           | <v x 1 x half>   | <v x 2 x half>   | <v x 4 x half>    | <v x 8 x half>    | <v x 16 x half>   | <v x 32 x half>   |
++-------------------+---------------+------------------+------------------+-------------------+-------------------+-------------------+-------------------+
+| bfloat            | N/A           | <v x 1 x bfloat> | <v x 2 x bfloat> | <v x 4 x bfloat>  | <v x 8 x bfloat>  | <v x 16 x bfloat> | <v x 32 x bfloat> |
++-------------------+---------------+------------------+------------------+-------------------+-------------------+-------------------+-------------------+
 
 (Read ``<v x k x ty>`` as ``<vscale x k x ty>``)