rename to more directly match WhichResultOut

Author: ginsbach

llvm/lib/Target/AArch64/AArch64PerfectShuffle.h

@@ -6710,41 +6710,41 @@ inline bool isTRNMask(ArrayRef<int> M, unsigned NumElts,
 
   // "Variant" refers to the distinction bwetween trn1 and trn2, while
   // "Order" refers to sequence of input registers (matching vs flipped).
-  bool Variant0Order0 = true; // WhichResultOut = 0, OperandOrderOut = 0
-  bool Variant1Order0 = true; // WhichResultOut = 1, OperandOrderOut = 0
-  bool Variant0Order1 = true; // WhichResultOut = 0, OperandOrderOut = 1
-  bool Variant1Order1 = true; // WhichResultOut = 1, OperandOrderOut = 1
+  bool Result0Order0 = true; // WhichResultOut = 0, OperandOrderOut = 0
+  bool Result1Order0 = true; // WhichResultOut = 1, OperandOrderOut = 0
+  bool Result0Order1 = true; // WhichResultOut = 0, OperandOrderOut = 1
+  bool Result1Order1 = true; // WhichResultOut = 1, OperandOrderOut = 1
   // Check all elements match.
   for (unsigned i = 0; i != NumElts; i += 2) {
     if (M[i] >= 0) {
       unsigned EvenElt = (unsigned)M[i];
       if (EvenElt != i)
-        Variant0Order0 = false;
+        Result0Order0 = false;
       if (EvenElt != i + 1)
-        Variant1Order0 = false;
+        Result1Order0 = false;
       if (EvenElt != NumElts + i)
-        Variant0Order1 = false;
+        Result0Order1 = false;
       if (EvenElt != NumElts + i + 1)
-        Variant1Order1 = false;
+        Result1Order1 = false;
     }
     if (M[i + 1] >= 0) {
       unsigned OddElt = (unsigned)M[i + 1];
       if (OddElt != NumElts + i)
-        Variant0Order0 = false;
+        Result0Order0 = false;
       if (OddElt != NumElts + i + 1)
-        Variant1Order0 = false;
+        Result1Order0 = false;
       if (OddElt != i)
-        Variant0Order1 = false;
+        Result0Order1 = false;
       if (OddElt != i + 1)
-        Variant1Order1 = false;
+        Result1Order1 = false;
     }
   }
 
-  if (Variant0Order0 + Variant1Order0 + Variant0Order1 + Variant1Order1 != 1)
+  if (Result0Order0 + Result1Order0 + Result0Order1 + Result1Order1 != 1)
     return false;
 
-  WhichResultOut = (Variant0Order0 || Variant0Order1) ? 0 : 1;
-  OperandOrderOut = (Variant0Order0 || Variant1Order0) ? 0 : 1;
+  WhichResultOut = (Result0Order0 || Result0Order1) ? 0 : 1;
+  OperandOrderOut = (Result0Order0 || Result1Order0) ? 0 : 1;
   return true;
 }