Address review comments

Author: dstutt

llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp

@@ -23,6 +23,7 @@
 #include "llvm/MC/MCExpr.h"
 #include "llvm/Support/AMDGPUMetadata.h"
 #include "llvm/Support/EndianStream.h"
+#include "llvm/Support/VersionTuple.h"
 
 using namespace llvm;
 using namespace llvm::AMDGPU;
@@ -260,8 +261,7 @@ void AMDGPUPALMetadata::setEntryPoint(unsigned CC, StringRef Name) {
       MsgPackDoc.getNode(Name, /*Copy=*/true);
 
   // For pal version 3.6 and above, entry_point is no longer required
-  if (getPALMajorVersion() < 3 ||
-      (getPALMajorVersion() == 3 && getPALMinorVersion() < 6)) {
+  if (getPALVersion() < VersionTuple(3, 6)) {
     // Set .entry_point which is defined
     // to be _amdgpu_<stage>_main and _amdgpu_cs_main for non-shader functions
     SmallString<16> EPName("_amdgpu_");
@@ -1056,6 +1056,10 @@ unsigned AMDGPUPALMetadata::getPALMajorVersion() { return getPALVersion(0); }
 
 unsigned AMDGPUPALMetadata::getPALMinorVersion() { return getPALVersion(1); }
 
+VersionTuple AMDGPUPALMetadata::getPALVersion() {
+  return VersionTuple(getPALVersion(0), getPALVersion(1));
+}
+
 // Set the field in a given .hardware_stages entry
 void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field, unsigned Val) {
   getHwStage(CC)[field] = Val;

llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.h

@@ -22,6 +22,7 @@ namespace llvm {
 
 class Module;
 class StringRef;
+class VersionTuple;
 
 class AMDGPUPALMetadata {
 public:
@@ -155,6 +156,7 @@ class AMDGPUPALMetadata {
 
   unsigned getPALMajorVersion();
   unsigned getPALMinorVersion();
+  VersionTuple getPALVersion();
 
   void setHwStage(unsigned CC, StringRef field, unsigned Val);
   void setHwStage(unsigned CC, StringRef field, bool Val);

llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.ll

@@ -180,32 +180,27 @@ define dllexport amdgpu_ps void @ps_shader() #1 {
 
 @LDS.GS = external addrspace(3) global [1 x i32], align 4
 
-define dllexport amdgpu_gs void @gs_shader() #2 {
+define dllexport amdgpu_gs void @gs_shader() {
   %ptr = getelementptr i32, ptr addrspace(3) @LDS.GS, i32 0
   store i32 0, ptr addrspace(3) %ptr, align 4
   ret void
 }
 
 @LDS.HS = external addrspace(3) global [1024 x i32], align 4
 
-define dllexport amdgpu_hs void @hs_shader() #2 {
+define dllexport amdgpu_hs void @hs_shader() {
   %ptr = getelementptr i32, ptr addrspace(3) @LDS.HS, i32 0
   store i32 0, ptr addrspace(3) %ptr, align 4
   ret void
 }
 
 !amdgpu.pal.metadata.msgpack = !{!0}
 
-; Function Attrs: nounwind willreturn memory(none)
 declare ptr addrspace(7) @lgc.buffer.desc.to.ptr(<4 x i32>) #1
-
-; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
-declare i64 @llvm.amdgcn.s.getpc() #2
-
-; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
+declare i64 @llvm.amdgcn.s.getpc()
 declare void @llvm.amdgcn.raw.buffer.store.i32(i32, <4 x i32>, i32, i32, i32 immarg) #3
 
-attributes #0 = { nounwind memory(readwrite) "amdgpu-flat-work-group-size"="1024,1024" "amdgpu-memory-bound"="false" "amdgpu-unroll-threshold"="700" "amdgpu-wave-limiter"="false" "amdgpu-work-group-info-arg-no"="4" "denormal-fp-math-f32"="preserve-sign" "target-features"=",+wavefrontsize64,+cumode" }
+attributes #0 = { nounwind memory(readwrite) "target-features"=",+wavefrontsize64,+cumode" }
 
 attributes #1 = { nounwind memory(readwrite) "InitialPSInputAddr"="36983" }
 

llvm/test/CodeGen/AMDGPU/pal-metadata-3.6.ll

@@ -180,32 +180,27 @@ define dllexport amdgpu_ps void @ps_shader() #1 {
 
 @LDS.GS = external addrspace(3) global [1 x i32], align 4
 
-define dllexport amdgpu_gs void @gs_shader() #2 {
+define dllexport amdgpu_gs void @gs_shader() {
   %ptr = getelementptr i32, ptr addrspace(3) @LDS.GS, i32 0
   store i32 0, ptr addrspace(3) %ptr, align 4
   ret void
 }
 
 @LDS.HS = external addrspace(3) global [1024 x i32], align 4
 
-define dllexport amdgpu_hs void @hs_shader() #2 {
+define dllexport amdgpu_hs void @hs_shader() {
   %ptr = getelementptr i32, ptr addrspace(3) @LDS.HS, i32 0
   store i32 0, ptr addrspace(3) %ptr, align 4
   ret void
 }
 
 !amdgpu.pal.metadata.msgpack = !{!0}
 
-; Function Attrs: nounwind willreturn memory(none)
 declare ptr addrspace(7) @lgc.buffer.desc.to.ptr(<4 x i32>) #1
-
-; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
-declare i64 @llvm.amdgcn.s.getpc() #2
-
-; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
+declare i64 @llvm.amdgcn.s.getpc()
 declare void @llvm.amdgcn.raw.buffer.store.i32(i32, <4 x i32>, i32, i32, i32 immarg) #3
 
-attributes #0 = { nounwind memory(readwrite) "amdgpu-flat-work-group-size"="1024,1024" "amdgpu-memory-bound"="false" "amdgpu-unroll-threshold"="700" "amdgpu-wave-limiter"="false" "amdgpu-work-group-info-arg-no"="4" "denormal-fp-math-f32"="preserve-sign" "target-features"=",+wavefrontsize64,+cumode" }
+attributes #0 = { nounwind memory(readwrite) "target-features"=",+wavefrontsize64,+cumode" }
 
 attributes #1 = { nounwind memory(readwrite) "InitialPSInputAddr"="36983" }