Skip to content

Commit 8400415

Browse files
committed
[CodeGen] Use VirtRegOrUnit in MachineTraceMetrics (NFC)
1 parent ef9a02c commit 8400415

File tree

2 files changed

+17
-13
lines changed

2 files changed

+17
-13
lines changed

llvm/include/llvm/CodeGen/MachineTraceMetrics.h

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -73,14 +73,14 @@ class TargetRegisterInfo;
7373
// direction instructions are scanned, it could be the operand that defined the
7474
// regunit, or the highest operand to read the regunit.
7575
struct LiveRegUnit {
76-
unsigned RegUnit;
76+
MCRegUnit RegUnit;
7777
unsigned Cycle = 0;
7878
const MachineInstr *MI = nullptr;
7979
unsigned Op = 0;
8080

8181
unsigned getSparseSetIndex() const { return RegUnit; }
8282

83-
LiveRegUnit(unsigned RU) : RegUnit(RU) {}
83+
explicit LiveRegUnit(MCRegUnit RU) : RegUnit(RU) {}
8484
};
8585

8686
/// Strategies for selecting traces.
@@ -156,13 +156,14 @@ class MachineTraceMetrics {
156156
/// successors.
157157
struct LiveInReg {
158158
/// The virtual register required, or a register unit.
159-
Register Reg;
159+
VirtRegOrUnit VRegOrUnit;
160160

161161
/// For virtual registers: Minimum height of the defining instruction.
162162
/// For regunits: Height of the highest user in the trace.
163163
unsigned Height;
164164

165-
LiveInReg(Register Reg, unsigned Height = 0) : Reg(Reg), Height(Height) {}
165+
LiveInReg(VirtRegOrUnit VRegOrUnit, unsigned Height = 0)
166+
: VRegOrUnit(VRegOrUnit), Height(Height) {}
166167
};
167168

168169
/// Per-basic block information that relates to a specific trace through the

llvm/lib/CodeGen/MachineTraceMetrics.cpp

Lines changed: 12 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -800,9 +800,10 @@ computeCrossBlockCriticalPath(const TraceBlockInfo &TBI) {
800800
assert(TBI.HasValidInstrHeights && "Missing height info");
801801
unsigned MaxLen = 0;
802802
for (const LiveInReg &LIR : TBI.LiveIns) {
803-
if (!LIR.Reg.isVirtual())
803+
if (!LIR.VRegOrUnit.isVirtualReg())
804804
continue;
805-
const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg);
805+
const MachineInstr *DefMI =
806+
MTM.MRI->getVRegDef(LIR.VRegOrUnit.asVirtualReg());
806807
// Ignore dependencies outside the current trace.
807808
const TraceBlockInfo &DefTBI = BlockInfo[DefMI->getParent()->getNumber()];
808809
if (!DefTBI.isUsefulDominator(TBI))
@@ -1020,7 +1021,7 @@ addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
10201021
return;
10211022
TraceBlockInfo &TBI = BlockInfo[MBB->getNumber()];
10221023
// Just add the register. The height will be updated later.
1023-
TBI.LiveIns.push_back(Reg);
1024+
TBI.LiveIns.push_back(VirtRegOrUnit(Reg));
10241025
}
10251026
}
10261027

@@ -1057,15 +1058,16 @@ computeInstrHeights(const MachineBasicBlock *MBB) {
10571058
if (MBB) {
10581059
TraceBlockInfo &TBI = BlockInfo[MBB->getNumber()];
10591060
for (LiveInReg &LI : TBI.LiveIns) {
1060-
if (LI.Reg.isVirtual()) {
1061+
if (LI.VRegOrUnit.isVirtualReg()) {
10611062
// For virtual registers, the def latency is included.
1062-
unsigned &Height = Heights[MTM.MRI->getVRegDef(LI.Reg)];
1063+
unsigned &Height =
1064+
Heights[MTM.MRI->getVRegDef(LI.VRegOrUnit.asVirtualReg())];
10631065
if (Height < LI.Height)
10641066
Height = LI.Height;
10651067
} else {
10661068
// For register units, the def latency is not included because we don't
10671069
// know the def yet.
1068-
RegUnits[LI.Reg.id()].Cycle = LI.Height;
1070+
RegUnits[LI.VRegOrUnit.asMCRegUnit()].Cycle = LI.Height;
10691071
}
10701072
}
10711073
}
@@ -1160,14 +1162,15 @@ computeInstrHeights(const MachineBasicBlock *MBB) {
11601162
// height because the final height isn't known until now.
11611163
LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " Live-ins:");
11621164
for (LiveInReg &LIR : TBI.LiveIns) {
1163-
const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg);
1165+
Register Reg = LIR.VRegOrUnit.asVirtualReg();
1166+
const MachineInstr *DefMI = MTM.MRI->getVRegDef(Reg);
11641167
LIR.Height = Heights.lookup(DefMI);
1165-
LLVM_DEBUG(dbgs() << ' ' << printReg(LIR.Reg) << '@' << LIR.Height);
1168+
LLVM_DEBUG(dbgs() << ' ' << printReg(Reg) << '@' << LIR.Height);
11661169
}
11671170

11681171
// Transfer the live regunits to the live-in list.
11691172
for (const LiveRegUnit &RU : RegUnits) {
1170-
TBI.LiveIns.push_back(LiveInReg(RU.RegUnit, RU.Cycle));
1173+
TBI.LiveIns.push_back(LiveInReg(VirtRegOrUnit(RU.RegUnit), RU.Cycle));
11711174
LLVM_DEBUG(dbgs() << ' ' << printRegUnit(RU.RegUnit, MTM.TRI) << '@'
11721175
<< RU.Cycle);
11731176
}

0 commit comments

Comments
 (0)