@@ -800,9 +800,10 @@ computeCrossBlockCriticalPath(const TraceBlockInfo &TBI) {
800800 assert (TBI.HasValidInstrHeights && " Missing height info" );
801801 unsigned MaxLen = 0 ;
802802 for (const LiveInReg &LIR : TBI.LiveIns ) {
803- if (!LIR.Reg . isVirtual ())
803+ if (!LIR.VRegOrUnit . isVirtualReg ())
804804 continue ;
805- const MachineInstr *DefMI = MTM.MRI ->getVRegDef (LIR.Reg );
805+ const MachineInstr *DefMI =
806+ MTM.MRI ->getVRegDef (LIR.VRegOrUnit .asVirtualReg ());
806807 // Ignore dependencies outside the current trace.
807808 const TraceBlockInfo &DefTBI = BlockInfo[DefMI->getParent ()->getNumber ()];
808809 if (!DefTBI.isUsefulDominator (TBI))
@@ -1020,7 +1021,7 @@ addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
10201021 return ;
10211022 TraceBlockInfo &TBI = BlockInfo[MBB->getNumber ()];
10221023 // Just add the register. The height will be updated later.
1023- TBI.LiveIns .push_back (Reg);
1024+ TBI.LiveIns .push_back (VirtRegOrUnit ( Reg) );
10241025 }
10251026}
10261027
@@ -1057,15 +1058,16 @@ computeInstrHeights(const MachineBasicBlock *MBB) {
10571058 if (MBB) {
10581059 TraceBlockInfo &TBI = BlockInfo[MBB->getNumber ()];
10591060 for (LiveInReg &LI : TBI.LiveIns ) {
1060- if (LI.Reg . isVirtual ()) {
1061+ if (LI.VRegOrUnit . isVirtualReg ()) {
10611062 // For virtual registers, the def latency is included.
1062- unsigned &Height = Heights[MTM.MRI ->getVRegDef (LI.Reg )];
1063+ unsigned &Height =
1064+ Heights[MTM.MRI ->getVRegDef (LI.VRegOrUnit .asVirtualReg ())];
10631065 if (Height < LI.Height )
10641066 Height = LI.Height ;
10651067 } else {
10661068 // For register units, the def latency is not included because we don't
10671069 // know the def yet.
1068- RegUnits[LI.Reg . id ()].Cycle = LI.Height ;
1070+ RegUnits[LI.VRegOrUnit . asMCRegUnit ()].Cycle = LI.Height ;
10691071 }
10701072 }
10711073 }
@@ -1160,14 +1162,15 @@ computeInstrHeights(const MachineBasicBlock *MBB) {
11601162 // height because the final height isn't known until now.
11611163 LLVM_DEBUG (dbgs () << printMBBReference (*MBB) << " Live-ins:" );
11621164 for (LiveInReg &LIR : TBI.LiveIns ) {
1163- const MachineInstr *DefMI = MTM.MRI ->getVRegDef (LIR.Reg );
1165+ Register Reg = LIR.VRegOrUnit .asVirtualReg ();
1166+ const MachineInstr *DefMI = MTM.MRI ->getVRegDef (Reg);
11641167 LIR.Height = Heights.lookup (DefMI);
1165- LLVM_DEBUG (dbgs () << ' ' << printReg (LIR. Reg ) << ' @' << LIR.Height );
1168+ LLVM_DEBUG (dbgs () << ' ' << printReg (Reg) << ' @' << LIR.Height );
11661169 }
11671170
11681171 // Transfer the live regunits to the live-in list.
11691172 for (const LiveRegUnit &RU : RegUnits) {
1170- TBI.LiveIns .push_back (LiveInReg (RU.RegUnit , RU.Cycle ));
1173+ TBI.LiveIns .push_back (LiveInReg (VirtRegOrUnit ( RU.RegUnit ) , RU.Cycle ));
11711174 LLVM_DEBUG (dbgs () << ' ' << printRegUnit (RU.RegUnit , MTM.TRI ) << ' @'
11721175 << RU.Cycle );
11731176 }
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