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nikicnikic
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[LowerTypeTests] Generate fshr for rotate pattern (#141735)
The canonical representation for a rotate right is fshr with two equal arguments, so generate that instead of a lshr/shl/or sequence.
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8 files changed

+47
-96
lines changed

8 files changed

+47
-96
lines changed

‎llvm/lib/Transforms/IPO/LowerTypeTests.cpp‎

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -779,15 +779,9 @@ Value *LowerTypeTestsModule::lowerTypeTestCall(Metadata *TypeId, CallInst *CI,
779779
// result, causing the comparison to fail if they are nonzero. The rotate
780780
// also conveniently gives us a bit offset to use during the load from
781781
// the bitset.
782-
Value *OffsetSHR =
783-
B.CreateLShr(PtrOffset, B.CreateZExt(TIL.AlignLog2, IntPtrTy));
784-
Value *OffsetSHL = B.CreateShl(
785-
PtrOffset, B.CreateZExt(
786-
ConstantExpr::getSub(
787-
ConstantInt::get(Int8Ty, DL.getPointerSizeInBits(0)),
788-
TIL.AlignLog2),
789-
IntPtrTy));
790-
Value *BitOffset = B.CreateOr(OffsetSHR, OffsetSHL);
782+
Value *BitOffset = B.CreateIntrinsic(
783+
IntPtrTy, Intrinsic::fshr,
784+
{PtrOffset, PtrOffset, B.CreateZExt(TIL.AlignLog2, IntPtrTy)});
791785

792786
Value *OffsetInRange = B.CreateICmpULE(BitOffset, TIL.SizeM1);
793787

‎llvm/test/ThinLTO/X86/cfi-devirt.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,7 @@ cont2:
9191
; CHECK-IR: br i1 {{.*}}, label %trap, label %cont2
9292

9393
; We still have to call it as virtual.
94-
; CHECK-IR: %call3 = tail call i32 %7
94+
; CHECK-IR: %call3 = tail call i32 %4
9595
%call3 = tail call i32 %5(ptr nonnull %obj, i32 %call)
9696
ret i32 %call3
9797
}

‎llvm/test/Transforms/LowerTypeTests/aarch64-jumptable.ll‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -42,11 +42,9 @@ define i1 @foo(ptr %p) {
4242
; AARCH64-SAME: (ptr [[P:%.*]]) {
4343
; AARCH64-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
4444
; AARCH64-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @.cfi.jumptable to i64)
45-
; AARCH64-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
46-
; AARCH64-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], 61
47-
; AARCH64-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
48-
; AARCH64-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], 1
49-
; AARCH64-NEXT: ret i1 [[TMP6]]
45+
; AARCH64-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 3)
46+
; AARCH64-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], 1
47+
; AARCH64-NEXT: ret i1 [[TMP4]]
5048
;
5149
;
5250
; AARCH64: Function Attrs: naked noinline

‎llvm/test/Transforms/LowerTypeTests/function-thumb-bti.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -33,8 +33,8 @@ define i1 @foo(ptr %p) {
3333
; branch instruction, 4 bytes each. For non-BTI, we shift right by 2,
3434
; because it's just the branch.
3535

36-
; BTI: lshr i64 {{.*}}, 3
37-
; NOBTI: lshr i64 {{.*}}, 2
36+
; BTI: @llvm.fshr.i64({{.*}}, i64 3)
37+
; NOBTI: @llvm.fshr.i64({{.*}}, i64 2)
3838

3939
; CHECK: define private void @.cfi.jumptable() [[ATTRS:#[0-9]+]]
4040

‎llvm/test/Transforms/LowerTypeTests/import.ll‎

Lines changed: 28 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -38,20 +38,15 @@ define i1 @allones7(ptr %p) {
3838
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
3939
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_allones7_global_addr to i64)
4040
; X86-NEXT: [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_allones7_align to i8) to i64
41-
; X86-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP2]], [[TMP3]]
42-
; X86-NEXT: [[TMP5:%.*]] = zext i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_allones7_align to i8)) to i64
43-
; X86-NEXT: [[TMP6:%.*]] = shl i64 [[TMP2]], [[TMP5]]
44-
; X86-NEXT: [[TMP7:%.*]] = or i64 [[TMP4]], [[TMP6]]
41+
; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 [[TMP3]])
4542
; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_allones7_size_m1 to i64)
4643
; X86-NEXT: ret i1 [[TMP8]]
4744
;
4845
; ARM-LABEL: define i1 @allones7(
4946
; ARM-SAME: ptr [[P:%.*]]) {
5047
; ARM-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
5148
; ARM-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_allones7_global_addr to i64)
52-
; ARM-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 1
53-
; ARM-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], 63
54-
; ARM-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
49+
; ARM-NEXT: [[TMP5:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 1)
5550
; ARM-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], 42
5651
; ARM-NEXT: ret i1 [[TMP6]]
5752
;
@@ -65,20 +60,15 @@ define i1 @allones32(ptr %p) {
6560
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
6661
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_allones32_global_addr to i64)
6762
; X86-NEXT: [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_allones32_align to i8) to i64
68-
; X86-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP2]], [[TMP3]]
69-
; X86-NEXT: [[TMP5:%.*]] = zext i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_allones32_align to i8)) to i64
70-
; X86-NEXT: [[TMP6:%.*]] = shl i64 [[TMP2]], [[TMP5]]
71-
; X86-NEXT: [[TMP7:%.*]] = or i64 [[TMP4]], [[TMP6]]
63+
; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 [[TMP3]])
7264
; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_allones32_size_m1 to i64)
7365
; X86-NEXT: ret i1 [[TMP8]]
7466
;
7567
; ARM-LABEL: define i1 @allones32(
7668
; ARM-SAME: ptr [[P:%.*]]) {
7769
; ARM-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
7870
; ARM-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_allones32_global_addr to i64)
79-
; ARM-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 2
80-
; ARM-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], 62
81-
; ARM-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
71+
; ARM-NEXT: [[TMP5:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 2)
8272
; ARM-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], 12345
8373
; ARM-NEXT: ret i1 [[TMP6]]
8474
;
@@ -92,38 +82,33 @@ define i1 @bytearray7(ptr %p) {
9282
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
9383
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_bytearray7_global_addr to i64)
9484
; X86-NEXT: [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_bytearray7_align to i8) to i64
95-
; X86-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP2]], [[TMP3]]
96-
; X86-NEXT: [[TMP5:%.*]] = zext i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_bytearray7_align to i8)) to i64
97-
; X86-NEXT: [[TMP6:%.*]] = shl i64 [[TMP2]], [[TMP5]]
98-
; X86-NEXT: [[TMP7:%.*]] = or i64 [[TMP4]], [[TMP6]]
85+
; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 [[TMP3]])
9986
; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_bytearray7_size_m1 to i64)
10087
; X86-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP14:%.*]]
101-
; X86: 9:
88+
; X86: 6:
10289
; X86-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[TMP7]]
10390
; X86-NEXT: [[TMP11:%.*]] = load i8, ptr [[TMP10]], align 1
10491
; X86-NEXT: [[TMP12:%.*]] = and i8 [[TMP11]], ptrtoint (ptr @__typeid_bytearray7_bit_mask to i8)
10592
; X86-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
10693
; X86-NEXT: br label [[TMP14]]
107-
; X86: 14:
94+
; X86: 11:
10895
; X86-NEXT: [[TMP15:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP13]], [[TMP9]] ]
10996
; X86-NEXT: ret i1 [[TMP15]]
11097
;
11198
; ARM-LABEL: define i1 @bytearray7(
11299
; ARM-SAME: ptr [[P:%.*]]) {
113100
; ARM-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
114101
; ARM-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_bytearray7_global_addr to i64)
115-
; ARM-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
116-
; ARM-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], 61
117-
; ARM-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
102+
; ARM-NEXT: [[TMP5:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 3)
118103
; ARM-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], 43
119104
; ARM-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP12:%.*]]
120-
; ARM: 7:
105+
; ARM: 5:
121106
; ARM-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[TMP5]]
122107
; ARM-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
123108
; ARM-NEXT: [[TMP10:%.*]] = and i8 [[TMP9]], ptrtoint (ptr inttoptr (i64 64 to ptr) to i8)
124109
; ARM-NEXT: [[TMP11:%.*]] = icmp ne i8 [[TMP10]], 0
125110
; ARM-NEXT: br label [[TMP12]]
126-
; ARM: 12:
111+
; ARM: 10:
127112
; ARM-NEXT: [[TMP13:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP11]], [[TMP7]] ]
128113
; ARM-NEXT: ret i1 [[TMP13]]
129114
;
@@ -137,38 +122,33 @@ define i1 @bytearray32(ptr %p) {
137122
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
138123
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_bytearray32_global_addr to i64)
139124
; X86-NEXT: [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_bytearray32_align to i8) to i64
140-
; X86-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP2]], [[TMP3]]
141-
; X86-NEXT: [[TMP5:%.*]] = zext i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_bytearray32_align to i8)) to i64
142-
; X86-NEXT: [[TMP6:%.*]] = shl i64 [[TMP2]], [[TMP5]]
143-
; X86-NEXT: [[TMP7:%.*]] = or i64 [[TMP4]], [[TMP6]]
125+
; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 [[TMP3]])
144126
; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_bytearray32_size_m1 to i64)
145127
; X86-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP14:%.*]]
146-
; X86: 9:
128+
; X86: 6:
147129
; X86-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr @__typeid_bytearray32_byte_array, i64 [[TMP7]]
148130
; X86-NEXT: [[TMP11:%.*]] = load i8, ptr [[TMP10]], align 1
149131
; X86-NEXT: [[TMP12:%.*]] = and i8 [[TMP11]], ptrtoint (ptr @__typeid_bytearray32_bit_mask to i8)
150132
; X86-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
151133
; X86-NEXT: br label [[TMP14]]
152-
; X86: 14:
134+
; X86: 11:
153135
; X86-NEXT: [[TMP15:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP13]], [[TMP9]] ]
154136
; X86-NEXT: ret i1 [[TMP15]]
155137
;
156138
; ARM-LABEL: define i1 @bytearray32(
157139
; ARM-SAME: ptr [[P:%.*]]) {
158140
; ARM-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
159141
; ARM-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_bytearray32_global_addr to i64)
160-
; ARM-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 4
161-
; ARM-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], 60
162-
; ARM-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
142+
; ARM-NEXT: [[TMP5:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 4)
163143
; ARM-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], 12346
164144
; ARM-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP12:%.*]]
165-
; ARM: 7:
145+
; ARM: 5:
166146
; ARM-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr @__typeid_bytearray32_byte_array, i64 [[TMP5]]
167147
; ARM-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
168148
; ARM-NEXT: [[TMP10:%.*]] = and i8 [[TMP9]], ptrtoint (ptr inttoptr (i64 128 to ptr) to i8)
169149
; ARM-NEXT: [[TMP11:%.*]] = icmp ne i8 [[TMP10]], 0
170150
; ARM-NEXT: br label [[TMP12]]
171-
; ARM: 12:
151+
; ARM: 10:
172152
; ARM-NEXT: [[TMP13:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP11]], [[TMP7]] ]
173153
; ARM-NEXT: ret i1 [[TMP13]]
174154
;
@@ -182,40 +162,35 @@ define i1 @inline5(ptr %p) {
182162
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
183163
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_inline5_global_addr to i64)
184164
; X86-NEXT: [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_inline5_align to i8) to i64
185-
; X86-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP2]], [[TMP3]]
186-
; X86-NEXT: [[TMP5:%.*]] = zext i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_inline5_align to i8)) to i64
187-
; X86-NEXT: [[TMP6:%.*]] = shl i64 [[TMP2]], [[TMP5]]
188-
; X86-NEXT: [[TMP7:%.*]] = or i64 [[TMP4]], [[TMP6]]
165+
; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 [[TMP3]])
189166
; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_inline5_size_m1 to i64)
190167
; X86-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP15:%.*]]
191-
; X86: 9:
168+
; X86: 6:
192169
; X86-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP7]] to i32
193170
; X86-NEXT: [[TMP11:%.*]] = and i32 [[TMP10]], 31
194171
; X86-NEXT: [[TMP12:%.*]] = shl i32 1, [[TMP11]]
195172
; X86-NEXT: [[TMP13:%.*]] = and i32 ptrtoint (ptr @__typeid_inline5_inline_bits to i32), [[TMP12]]
196173
; X86-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
197174
; X86-NEXT: br label [[TMP15]]
198-
; X86: 15:
175+
; X86: 12:
199176
; X86-NEXT: [[TMP16:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP14]], [[TMP9]] ]
200177
; X86-NEXT: ret i1 [[TMP16]]
201178
;
202179
; ARM-LABEL: define i1 @inline5(
203180
; ARM-SAME: ptr [[P:%.*]]) {
204181
; ARM-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
205182
; ARM-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_inline5_global_addr to i64)
206-
; ARM-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 5
207-
; ARM-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], 59
208-
; ARM-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
183+
; ARM-NEXT: [[TMP5:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 5)
209184
; ARM-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], 31
210185
; ARM-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP13:%.*]]
211-
; ARM: 7:
186+
; ARM: 5:
212187
; ARM-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP5]] to i32
213188
; ARM-NEXT: [[TMP9:%.*]] = and i32 [[TMP8]], 31
214189
; ARM-NEXT: [[TMP10:%.*]] = shl i32 1, [[TMP9]]
215190
; ARM-NEXT: [[TMP11:%.*]] = and i32 123, [[TMP10]]
216191
; ARM-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
217192
; ARM-NEXT: br label [[TMP13]]
218-
; ARM: 13:
193+
; ARM: 11:
219194
; ARM-NEXT: [[TMP14:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP12]], [[TMP7]] ]
220195
; ARM-NEXT: ret i1 [[TMP14]]
221196
;
@@ -229,38 +204,33 @@ define i1 @inline6(ptr %p) {
229204
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
230205
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_inline6_global_addr to i64)
231206
; X86-NEXT: [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_inline6_align to i8) to i64
232-
; X86-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP2]], [[TMP3]]
233-
; X86-NEXT: [[TMP5:%.*]] = zext i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_inline6_align to i8)) to i64
234-
; X86-NEXT: [[TMP6:%.*]] = shl i64 [[TMP2]], [[TMP5]]
235-
; X86-NEXT: [[TMP7:%.*]] = or i64 [[TMP4]], [[TMP6]]
207+
; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 [[TMP3]])
236208
; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_inline6_size_m1 to i64)
237209
; X86-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP14:%.*]]
238-
; X86: 9:
210+
; X86: 6:
239211
; X86-NEXT: [[TMP10:%.*]] = and i64 [[TMP7]], 63
240212
; X86-NEXT: [[TMP11:%.*]] = shl i64 1, [[TMP10]]
241213
; X86-NEXT: [[TMP12:%.*]] = and i64 ptrtoint (ptr @__typeid_inline6_inline_bits to i64), [[TMP11]]
242214
; X86-NEXT: [[TMP13:%.*]] = icmp ne i64 [[TMP12]], 0
243215
; X86-NEXT: br label [[TMP14]]
244-
; X86: 14:
216+
; X86: 11:
245217
; X86-NEXT: [[TMP15:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP13]], [[TMP9]] ]
246218
; X86-NEXT: ret i1 [[TMP15]]
247219
;
248220
; ARM-LABEL: define i1 @inline6(
249221
; ARM-SAME: ptr [[P:%.*]]) {
250222
; ARM-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
251223
; ARM-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_inline6_global_addr to i64)
252-
; ARM-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 6
253-
; ARM-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], 58
254-
; ARM-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
224+
; ARM-NEXT: [[TMP5:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 6)
255225
; ARM-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], 63
256226
; ARM-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP12:%.*]]
257-
; ARM: 7:
227+
; ARM: 5:
258228
; ARM-NEXT: [[TMP8:%.*]] = and i64 [[TMP5]], 63
259229
; ARM-NEXT: [[TMP9:%.*]] = shl i64 1, [[TMP8]]
260230
; ARM-NEXT: [[TMP10:%.*]] = and i64 1000000000000, [[TMP9]]
261231
; ARM-NEXT: [[TMP11:%.*]] = icmp ne i64 [[TMP10]], 0
262232
; ARM-NEXT: br label [[TMP12]]
263-
; ARM: 12:
233+
; ARM: 10:
264234
; ARM-NEXT: [[TMP13:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP11]], [[TMP7]] ]
265235
; ARM-NEXT: ret i1 [[TMP13]]
266236
;

‎llvm/test/Transforms/LowerTypeTests/simple.ll‎

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -50,9 +50,7 @@ define i1 @foo(ptr %p) {
5050

5151
; CHECK: [[R1:%[^ ]*]] = ptrtoint ptr %p to i32
5252
; CHECK: [[R2:%[^ ]*]] = sub i32 [[R1]], ptrtoint (ptr [[G]] to i32)
53-
; CHECK: [[R3:%[^ ]*]] = lshr i32 [[R2]], 2
54-
; CHECK: [[R4:%[^ ]*]] = shl i32 [[R2]], 30
55-
; CHECK: [[R5:%[^ ]*]] = or i32 [[R3]], [[R4]]
53+
; CHECK: [[R5:%[^ ]*]] = call i32 @llvm.fshr.i32(i32 [[R2]], i32 [[R2]], i32 2)
5654
; CHECK: [[R6:%[^ ]*]] = icmp ule i32 [[R5]], 67
5755
; CHECK: br i1 [[R6]]
5856

@@ -75,9 +73,7 @@ define i1 @foo(ptr %p) {
7573
define i1 @bar(ptr %p) {
7674
; CHECK: [[S1:%[^ ]*]] = ptrtoint ptr %p to i32
7775
; CHECK: [[S2:%[^ ]*]] = sub i32 [[S1]], ptrtoint (ptr getelementptr (i8, ptr [[G]], i32 4) to i32)
78-
; CHECK: [[S3:%[^ ]*]] = lshr i32 [[S2]], 8
79-
; CHECK: [[S4:%[^ ]*]] = shl i32 [[S2]], 24
80-
; CHECK: [[S5:%[^ ]*]] = or i32 [[S3]], [[S4]]
76+
; CHECK: [[S5:%[^ ]*]] = call i32 @llvm.fshr.i32(i32 [[S2]], i32 [[S2]], i32 8)
8177
; CHECK: [[S6:%[^ ]*]] = icmp ule i32 [[S5]], 1
8278
%x = call i1 @llvm.type.test(ptr %p, metadata !"typeid2")
8379

@@ -89,9 +85,7 @@ define i1 @bar(ptr %p) {
8985
define i1 @baz(ptr %p) {
9086
; CHECK: [[T1:%[^ ]*]] = ptrtoint ptr %p to i32
9187
; CHECK: [[T2:%[^ ]*]] = sub i32 [[T1]], ptrtoint (ptr [[G]] to i32)
92-
; CHECK: [[T3:%[^ ]*]] = lshr i32 [[T2]], 2
93-
; CHECK: [[T4:%[^ ]*]] = shl i32 [[T2]], 30
94-
; CHECK: [[T5:%[^ ]*]] = or i32 [[T3]], [[T4]]
88+
; CHECK: [[T5:%[^ ]*]] = call i32 @llvm.fshr.i32(i32 [[T2]], i32 [[T2]], i32 2)
9589
; CHECK: [[T6:%[^ ]*]] = icmp ule i32 [[T5]], 65
9690
; CHECK: br i1 [[T6]]
9791

‎llvm/test/Transforms/LowerTypeTests/simplify.ll‎

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -12,13 +12,10 @@ define i1 @bytearray7(ptr %p) {
1212
; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
1313
; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_bytearray7_global_addr to i64)
1414
; CHECK-NEXT: [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_bytearray7_align to i8) to i64
15-
; CHECK-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP2]], [[TMP3]]
16-
; CHECK-NEXT: [[TMP5:%.*]] = zext i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_bytearray7_align to i8)) to i64
17-
; CHECK-NEXT: [[TMP6:%.*]] = shl i64 [[TMP2]], [[TMP5]]
18-
; CHECK-NEXT: [[TMP7:%.*]] = or i64 [[TMP4]], [[TMP6]]
15+
; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 [[TMP3]])
1916
; CHECK-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_bytearray7_size_m1 to i64)
2017
; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[F:%.*]]
21-
; CHECK: 9:
18+
; CHECK: 6:
2219
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[TMP7]]
2320
; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr [[TMP10]], align 1
2421
; CHECK-NEXT: [[TMP12:%.*]] = and i8 [[TMP11]], ptrtoint (ptr @__typeid_bytearray7_bit_mask to i8)

‎llvm/test/Transforms/MergeFunc/cfi-thunk-merging.ll‎

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -182,17 +182,15 @@ attributes #3 = { noreturn nounwind }
182182
; LOWERTYPETESTS-NEXT: [[TMP2:%.*]] = load ptr, ptr [[FP]], align 8
183183
; LOWERTYPETESTS-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[TMP2]] to i64
184184
; LOWERTYPETESTS-NEXT: [[TMP4:%.*]] = sub i64 [[TMP3]], ptrtoint (ptr @.cfi.jumptable to i64)
185-
; LOWERTYPETESTS-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP4]], 3
186-
; LOWERTYPETESTS-NEXT: [[TMP6:%.*]] = shl i64 [[TMP4]], 61
187-
; LOWERTYPETESTS-NEXT: [[TMP7:%.*]] = or i64 [[TMP5]], [[TMP6]]
188-
; LOWERTYPETESTS-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], 1
189-
; LOWERTYPETESTS-NEXT: br i1 [[TMP8]], label [[CONT:%.*]], label [[TRAP:%.*]], !nosanitize [[META4:![0-9]+]]
185+
; LOWERTYPETESTS-NEXT: [[TMP5:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP4]], i64 [[TMP4]], i64 3)
186+
; LOWERTYPETESTS-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], 1
187+
; LOWERTYPETESTS-NEXT: br i1 [[TMP6]], label [[CONT:%.*]], label [[TRAP:%.*]], !nosanitize [[META4:![0-9]+]]
190188
; LOWERTYPETESTS: trap:
191189
; LOWERTYPETESTS-NEXT: call void @llvm.ubsantrap(i8 2) #[[ATTR4:[0-9]+]], !nosanitize [[META4]]
192190
; LOWERTYPETESTS-NEXT: unreachable, !nosanitize [[META4]]
193191
; LOWERTYPETESTS: cont:
194-
; LOWERTYPETESTS-NEXT: [[TMP9:%.*]] = load i32, ptr [[B_ADDR]], align 4
195-
; LOWERTYPETESTS-NEXT: [[CALL:%.*]] = call i32 [[TMP2]](i32 noundef [[TMP9]])
192+
; LOWERTYPETESTS-NEXT: [[TMP7:%.*]] = load i32, ptr [[B_ADDR]], align 4
193+
; LOWERTYPETESTS-NEXT: [[CALL:%.*]] = call i32 [[TMP2]](i32 noundef [[TMP7]])
196194
; LOWERTYPETESTS-NEXT: ret i32 [[CALL]]
197195
;
198196
;

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