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V-FEXrtV-FEXrt
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cleanup
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3 files changed

+18
-20
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‎llvm/lib/Target/DirectX/DXIL.td‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -627,7 +627,6 @@ def FirstbitLo : DXILOp<32, unaryBits> {
627627
let overloads =
628628
[Overloads<DXIL1_0, [Int16Ty, Int32Ty, Int64Ty]>];
629629
let stages = [Stages<DXIL1_0, [all_stages]>];
630-
// TODO: check these
631630
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
632631
}
633632

‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp‎

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2908,7 +2908,6 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
29082908
case Intrinsic::spv_firstbitshigh: // There is no CL equivalent of FindSMsb
29092909
return selectFirstBitHigh(ResVReg, ResType, I, /*IsSigned=*/true);
29102910
case Intrinsic::spv_firstbitlow: // There is no CL equivlent of FindILsb
2911-
// (true?)
29122911
return selectFirstBitLow(ResVReg, ResType, I);
29132912
case Intrinsic::spv_group_memory_barrier_with_group_sync: {
29142913
bool Result = true;
@@ -3382,7 +3381,7 @@ bool SPIRVInstructionSelector::selectFirstBitLow64(Register ResVReg,
33823381
// Per the spec, repeat the vector if only one vec is needed
33833382
.addUse(FBLReg);
33843383

3385-
// high bits are store in even indexes. Extract them from FBLReg
3384+
// high bits are stored in even indexes. Extract them from FBLReg
33863385
for (unsigned j = 0; j < ComponentCount * 2; j += 2) {
33873386
MIB.addImm(j);
33883387
}
@@ -3396,14 +3395,14 @@ bool SPIRVInstructionSelector::selectFirstBitLow64(Register ResVReg,
33963395
// Per the spec, repeat the vector if only one vec is needed
33973396
.addUse(FBLReg);
33983397

3399-
// low bits are store in odd indexes. Extract them from FBLReg
3398+
// low bits are stored in odd indexes. Extract them from FBLReg
34003399
for (unsigned j = 1; j < ComponentCount * 2; j += 2) {
34013400
MIB.addImm(j);
34023401
}
34033402
Result = Result && MIB.constrainAllUses(TII, TRI, RBI);
34043403
}
34053404

3406-
// 4. Check if result of each bottom 32 bits is == -1
3405+
// 4. Check the result. When low bits == -1 use high, otherwise use low
34073406
SPIRVType *BoolType = GR.getOrCreateSPIRVBoolType(I, TII);
34083407
Register NegOneReg;
34093408
Register Reg0;
@@ -3429,7 +3428,7 @@ bool SPIRVInstructionSelector::selectFirstBitLow64(Register ResVReg,
34293428
AddOp = SPIRV::OpIAddV;
34303429
}
34313430

3432-
// Check if the low bits are == -1; true if -1
3431+
// Check if the low bits are == -1
34333432
Register BReg = MRI->createVirtualRegister(GR.getRegClass(BoolType));
34343433
Result = Result && selectNAryOpWithSrcs(BReg, BoolType, I,
34353434
{LowReg, NegOneReg}, SPIRV::OpIEqual);
@@ -3439,7 +3438,7 @@ bool SPIRVInstructionSelector::selectFirstBitLow64(Register ResVReg,
34393438
Result = Result && selectNAryOpWithSrcs(TmpReg, ResType, I,
34403439
{BReg, HighReg, LowReg}, SelectOp);
34413440

3442-
// Add 32 for high bits, 0 for low bits
3441+
// 5. Add 32 when high bits are used, otherwise 0 for low bits
34433442
Register ValReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
34443443
Result = Result && selectNAryOpWithSrcs(ValReg, ResType, I,
34453444
{BReg, Reg32, Reg0}, SelectOp);

‎llvm/test/CodeGen/SPIRV/hlsl-intrinsics/firstbitlow.ll‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -6,13 +6,13 @@
66
; CHECK-DAG: [[u32_t:%.+]] = OpTypeInt 32 0
77
; CHECK-DAG: [[u32x2_t:%.+]] = OpTypeVector [[u32_t]] 2
88
; CHECK-DAG: [[u32x4_t:%.+]] = OpTypeVector [[u32_t]] 4
9-
; CHECK-DAG: [[const_zero:%.*]] = OpConstant [[u32_t]] 0
10-
; CHECK-DAG: [[const_zerox2:%.*]] = OpConstantComposite [[u32x2_t]] [[const_zero]] [[const_zero]]
11-
; CHECK-DAG: [[const_one:%.*]] = OpConstant [[u32_t]] 1
12-
; CHECK-DAG: [[const_thirty_two:%.*]] = OpConstant [[u32_t]] 32
13-
; CHECK-DAG: [[const_thirty_twox2:%.*]] = OpConstantComposite [[u32x2_t]] [[const_thirty_two]] [[const_thirty_two]]
14-
; CHECK-DAG: [[const_neg_one:%.*]] = OpConstant [[u32_t]] 4294967295
15-
; CHECK-DAG: [[const_neg_onex2:%.*]] = OpConstantComposite [[u32x2_t]] [[const_neg_one]] [[const_neg_one]]
9+
; CHECK-DAG: [[const_0:%.*]] = OpConstant [[u32_t]] 0
10+
; CHECK-DAG: [[const_0x2:%.*]] = OpConstantComposite [[u32x2_t]] [[const_0]] [[const_0]]
11+
; CHECK-DAG: [[const_1:%.*]] = OpConstant [[u32_t]] 1
12+
; CHECK-DAG: [[const_32:%.*]] = OpConstant [[u32_t]] 32
13+
; CHECK-DAG: [[const_32x2:%.*]] = OpConstantComposite [[u32x2_t]] [[const_32]] [[const_32]]
14+
; CHECK-DAG: [[const_neg1:%.*]] = OpConstant [[u32_t]] 4294967295
15+
; CHECK-DAG: [[const_neg1x2:%.*]] = OpConstantComposite [[u32x2_t]] [[const_neg1]] [[const_neg1]]
1616
; CHECK-DAG: [[u16_t:%.+]] = OpTypeInt 16 0
1717
; CHECK-DAG: [[u16x2_t:%.+]] = OpTypeVector [[u16_t]] 2
1818
; CHECK-DAG: [[u64_t:%.+]] = OpTypeInt 64 0
@@ -68,11 +68,11 @@ entry:
6868
; CHECK: [[a64:%.+]] = OpFunctionParameter [[u64_t]]
6969
; CHECK: [[a32x2:%.+]] = OpBitcast [[u32x2_t]] [[a64]]
7070
; CHECK: [[lsb_bits:%.+]] = OpExtInst [[u32x2_t]] [[glsl_450_ext]] FindILsb [[a32x2]]
71-
; CHECK: [[high_bits:%.+]] = OpVectorExtractDynamic [[u32_t]] [[lsb_bits]] [[const_zero]]
72-
; CHECK: [[low_bits:%.+]] = OpVectorExtractDynamic [[u32_t]] [[lsb_bits]] [[const_one]]
73-
; CHECK: [[should_use_high:%.+]] = OpIEqual [[bool_t]] [[low_bits]] [[const_neg_one]]
71+
; CHECK: [[high_bits:%.+]] = OpVectorExtractDynamic [[u32_t]] [[lsb_bits]] [[const_0]]
72+
; CHECK: [[low_bits:%.+]] = OpVectorExtractDynamic [[u32_t]] [[lsb_bits]] [[const_1]]
73+
; CHECK: [[should_use_high:%.+]] = OpIEqual [[bool_t]] [[low_bits]] [[const_neg1]]
7474
; CHECK: [[ans_bits:%.+]] = OpSelect [[u32_t]] [[should_use_high]] [[high_bits]] [[low_bits]]
75-
; CHECK: [[ans_offset:%.+]] = OpSelect [[u32_t]] [[should_use_high]] [[const_thirty_two]] [[const_zero]]
75+
; CHECK: [[ans_offset:%.+]] = OpSelect [[u32_t]] [[should_use_high]] [[const_32]] [[const_0]]
7676
; CHECK: [[ret:%.+]] = OpIAdd [[u32_t]] [[ans_offset]] [[ans_bits]]
7777
; CHECK: OpReturnValue [[ret]]
7878
%elt.firstbitlow = call i32 @llvm.spv.firstbitlow.i64(i64 %a)
@@ -87,9 +87,9 @@ entry:
8787
; CHECK: [[lsb_bits:%.+]] = OpExtInst [[u32x4_t]] [[glsl_450_ext]] FindILsb [[a32x4]]
8888
; CHECK: [[high_bits:%.+]] = OpVectorShuffle [[u32x2_t]] [[lsb_bits]] [[lsb_bits]] 0 2
8989
; CHECK: [[low_bits:%.+]] = OpVectorShuffle [[u32x2_t]] [[lsb_bits]] [[lsb_bits]] 1 3
90-
; CHECK: [[should_use_high:%.+]] = OpIEqual [[boolx2_t]] [[low_bits]] [[const_neg_onex2]]
90+
; CHECK: [[should_use_high:%.+]] = OpIEqual [[boolx2_t]] [[low_bits]] [[const_neg1x2]]
9191
; CHECK: [[ans_bits:%.+]] = OpSelect [[u32x2_t]] [[should_use_high]] [[high_bits]] [[low_bits]]
92-
; CHECK: [[ans_offset:%.+]] = OpSelect [[u32x2_t]] [[should_use_high]] [[const_thirty_twox2]] [[const_zerox2]]
92+
; CHECK: [[ans_offset:%.+]] = OpSelect [[u32x2_t]] [[should_use_high]] [[const_32x2]] [[const_0x2]]
9393
; CHECK: [[ret:%.+]] = OpIAdd [[u32x2_t]] [[ans_offset]] [[ans_bits]]
9494
; CHECK: OpReturnValue [[ret]]
9595
%elt.firstbitlow = call <2 x i32> @llvm.spv.firstbitlow.v2i64(<2 x i64> %a)

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