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[LoongArch] Pre-commit tests for vecreduce_and/or/... (#154879)
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‎llvm/test/CodeGen/LoongArch/lasx/vec-reduce-and.ll‎

Lines changed: 95 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s
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define void @vec_reduce_and_v32i8(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_and_v32i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
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; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 228
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvsrli.d $xr1, $xr1, 32
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 14
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.b $xr1, $xr1, 1
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.b $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <32 x i8>, ptr %src
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%res = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %v)
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store i8 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_and_v16i16(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_and_v16i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
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; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 228
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 14
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.h $xr1, $xr1, 1
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.h $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <16 x i16>, ptr %src
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%res = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %v)
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store i16 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_and_v8i32(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_and_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
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; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 228
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 14
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.w $xr1, $xr1, 1
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <8 x i32>, ptr %src
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%res = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %v)
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store i32 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_and_v4i64(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_and_v4i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
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; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI3_0)
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; CHECK-NEXT: xvpermi.d $xr2, $xr0, 78
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; CHECK-NEXT: xvshuf.d $xr1, $xr0, $xr2
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.d $xr1, $xr1, 1
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.d $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <4 x i64>, ptr %src
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%res = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %v)
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store i64 %res, ptr %dst
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ret void
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}
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‎llvm/test/CodeGen/LoongArch/lasx/vec-reduce-or.ll‎

Lines changed: 95 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s
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define void @vec_reduce_or_v32i8(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_or_v32i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
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; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 228
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvsrli.d $xr1, $xr1, 32
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 14
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.b $xr1, $xr1, 1
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.b $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <32 x i8>, ptr %src
26+
%res = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> %v)
27+
store i8 %res, ptr %dst
28+
ret void
29+
}
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define void @vec_reduce_or_v16i16(ptr %src, ptr %dst) nounwind {
32+
; CHECK-LABEL: vec_reduce_or_v16i16:
33+
; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
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; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 228
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 14
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.h $xr1, $xr1, 1
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.h $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <16 x i16>, ptr %src
50+
%res = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %v)
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store i16 %res, ptr %dst
52+
ret void
53+
}
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define void @vec_reduce_or_v8i32(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_or_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
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; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 228
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 14
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.w $xr1, $xr1, 1
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <8 x i32>, ptr %src
71+
%res = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %v)
72+
store i32 %res, ptr %dst
73+
ret void
74+
}
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define void @vec_reduce_or_v4i64(ptr %src, ptr %dst) nounwind {
77+
; CHECK-LABEL: vec_reduce_or_v4i64:
78+
; CHECK: # %bb.0:
79+
; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
81+
; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI3_0)
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; CHECK-NEXT: xvpermi.d $xr2, $xr0, 78
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; CHECK-NEXT: xvshuf.d $xr1, $xr0, $xr2
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.d $xr1, $xr1, 1
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; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.d $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <4 x i64>, ptr %src
91+
%res = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %v)
92+
store i64 %res, ptr %dst
93+
ret void
94+
}
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‎llvm/test/CodeGen/LoongArch/lasx/vec-reduce-smax.ll‎

Lines changed: 95 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,95 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s
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4+
define void @vec_reduce_smax_v32i8(ptr %src, ptr %dst) nounwind {
5+
; CHECK-LABEL: vec_reduce_smax_v32i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
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; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 228
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; CHECK-NEXT: xvmax.b $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
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; CHECK-NEXT: xvmax.b $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvsrli.d $xr1, $xr1, 32
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; CHECK-NEXT: xvmax.b $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
18+
; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 14
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; CHECK-NEXT: xvmax.b $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.b $xr1, $xr1, 1
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; CHECK-NEXT: xvmax.b $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.b $xr0, $a1, 0, 0
24+
; CHECK-NEXT: ret
25+
%v = load <32 x i8>, ptr %src
26+
%res = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> %v)
27+
store i8 %res, ptr %dst
28+
ret void
29+
}
30+
31+
define void @vec_reduce_smax_v16i16(ptr %src, ptr %dst) nounwind {
32+
; CHECK-LABEL: vec_reduce_smax_v16i16:
33+
; CHECK: # %bb.0:
34+
; CHECK-NEXT: xvld $xr0, $a0, 0
35+
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
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; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 228
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; CHECK-NEXT: xvmax.h $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
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; CHECK-NEXT: xvmax.h $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
42+
; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 14
43+
; CHECK-NEXT: xvmax.h $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
45+
; CHECK-NEXT: xvrepl128vei.h $xr1, $xr1, 1
46+
; CHECK-NEXT: xvmax.h $xr0, $xr0, $xr1
47+
; CHECK-NEXT: xvstelm.h $xr0, $a1, 0, 0
48+
; CHECK-NEXT: ret
49+
%v = load <16 x i16>, ptr %src
50+
%res = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> %v)
51+
store i16 %res, ptr %dst
52+
ret void
53+
}
54+
55+
define void @vec_reduce_smax_v8i32(ptr %src, ptr %dst) nounwind {
56+
; CHECK-LABEL: vec_reduce_smax_v8i32:
57+
; CHECK: # %bb.0:
58+
; CHECK-NEXT: xvld $xr0, $a0, 0
59+
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
60+
; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 228
61+
; CHECK-NEXT: xvmax.w $xr0, $xr0, $xr1
62+
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
63+
; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 14
64+
; CHECK-NEXT: xvmax.w $xr0, $xr0, $xr1
65+
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
66+
; CHECK-NEXT: xvrepl128vei.w $xr1, $xr1, 1
67+
; CHECK-NEXT: xvmax.w $xr0, $xr0, $xr1
68+
; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0
69+
; CHECK-NEXT: ret
70+
%v = load <8 x i32>, ptr %src
71+
%res = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> %v)
72+
store i32 %res, ptr %dst
73+
ret void
74+
}
75+
76+
define void @vec_reduce_smax_v4i64(ptr %src, ptr %dst) nounwind {
77+
; CHECK-LABEL: vec_reduce_smax_v4i64:
78+
; CHECK: # %bb.0:
79+
; CHECK-NEXT: xvld $xr0, $a0, 0
80+
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
81+
; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI3_0)
82+
; CHECK-NEXT: xvpermi.d $xr2, $xr0, 78
83+
; CHECK-NEXT: xvshuf.d $xr1, $xr0, $xr2
84+
; CHECK-NEXT: xvmax.d $xr0, $xr0, $xr1
85+
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
86+
; CHECK-NEXT: xvrepl128vei.d $xr1, $xr1, 1
87+
; CHECK-NEXT: xvmax.d $xr0, $xr0, $xr1
88+
; CHECK-NEXT: xvstelm.d $xr0, $a1, 0, 0
89+
; CHECK-NEXT: ret
90+
%v = load <4 x i64>, ptr %src
91+
%res = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> %v)
92+
store i64 %res, ptr %dst
93+
ret void
94+
}
95+

‎llvm/test/CodeGen/LoongArch/lasx/vec-reduce-smin.ll‎

Lines changed: 95 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,95 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s
3+
4+
define void @vec_reduce_smin_v32i8(ptr %src, ptr %dst) nounwind {
5+
; CHECK-LABEL: vec_reduce_smin_v32i8:
6+
; CHECK: # %bb.0:
7+
; CHECK-NEXT: xvld $xr0, $a0, 0
8+
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
9+
; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 228
10+
; CHECK-NEXT: xvmin.b $xr0, $xr0, $xr1
11+
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
12+
; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
13+
; CHECK-NEXT: xvmin.b $xr0, $xr0, $xr1
14+
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
15+
; CHECK-NEXT: xvsrli.d $xr1, $xr1, 32
16+
; CHECK-NEXT: xvmin.b $xr0, $xr0, $xr1
17+
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
18+
; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 14
19+
; CHECK-NEXT: xvmin.b $xr0, $xr0, $xr1
20+
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
21+
; CHECK-NEXT: xvrepl128vei.b $xr1, $xr1, 1
22+
; CHECK-NEXT: xvmin.b $xr0, $xr0, $xr1
23+
; CHECK-NEXT: xvstelm.b $xr0, $a1, 0, 0
24+
; CHECK-NEXT: ret
25+
%v = load <32 x i8>, ptr %src
26+
%res = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> %v)
27+
store i8 %res, ptr %dst
28+
ret void
29+
}
30+
31+
define void @vec_reduce_smin_v16i16(ptr %src, ptr %dst) nounwind {
32+
; CHECK-LABEL: vec_reduce_smin_v16i16:
33+
; CHECK: # %bb.0:
34+
; CHECK-NEXT: xvld $xr0, $a0, 0
35+
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
36+
; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 228
37+
; CHECK-NEXT: xvmin.h $xr0, $xr0, $xr1
38+
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
39+
; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8
40+
; CHECK-NEXT: xvmin.h $xr0, $xr0, $xr1
41+
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
42+
; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 14
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; CHECK-NEXT: xvmin.h $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.h $xr1, $xr1, 1
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; CHECK-NEXT: xvmin.h $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.h $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <16 x i16>, ptr %src
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%res = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> %v)
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store i16 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_smin_v8i32(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_smin_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78
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; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 228
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; CHECK-NEXT: xvmin.w $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 14
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; CHECK-NEXT: xvmin.w $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.w $xr1, $xr1, 1
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; CHECK-NEXT: xvmin.w $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <8 x i32>, ptr %src
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%res = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> %v)
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store i32 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_smin_v4i64(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_smin_v4i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
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; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI3_0)
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; CHECK-NEXT: xvpermi.d $xr2, $xr0, 78
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; CHECK-NEXT: xvshuf.d $xr1, $xr0, $xr2
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; CHECK-NEXT: xvmin.d $xr0, $xr0, $xr1
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; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.d $xr1, $xr1, 1
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; CHECK-NEXT: xvmin.d $xr0, $xr0, $xr1
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; CHECK-NEXT: xvstelm.d $xr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <4 x i64>, ptr %src
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%res = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> %v)
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store i64 %res, ptr %dst
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ret void
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}
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