@@ -2811,14 +2811,16 @@ bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
28112811 unsigned selectOp;
28122812 unsigned addOp;
28132813 if (isScalarRes) {
2814- NegOneReg = GR.getOrCreateConstInt (-1 , I, ResType, TII, ZeroAsNull);
2814+ NegOneReg =
2815+ GR.getOrCreateConstInt ((unsigned )-1 , I, ResType, TII, ZeroAsNull);
28152816 Reg0 = GR.getOrCreateConstInt (0 , I, ResType, TII, ZeroAsNull);
28162817 Reg32 = GR.getOrCreateConstInt (32 , I, ResType, TII, ZeroAsNull);
28172818 selectOp = SPIRV::OpSelectSISCond;
28182819 addOp = SPIRV::OpIAddS;
28192820 } else {
28202821 BoolType = GR.getOrCreateSPIRVVectorType (BoolType, count, MIRBuilder);
2821- NegOneReg = GR.getOrCreateConstVector (-1 , I, ResType, TII, ZeroAsNull);
2822+ NegOneReg =
2823+ GR.getOrCreateConstVector ((unsigned )-1 , I, ResType, TII, ZeroAsNull);
28222824 Reg0 = GR.getOrCreateConstVector (0 , I, ResType, TII, ZeroAsNull);
28232825 Reg32 = GR.getOrCreateConstVector (32 , I, ResType, TII, ZeroAsNull);
28242826 selectOp = SPIRV::OpSelectVIVCond;
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