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1 parent 0ae224f commit 84b8e76Copy full SHA for 84b8e76
mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
@@ -1685,9 +1685,9 @@ NVVM::IIDArgsWithTypes CpAsyncBulkTensorReduceOp::getIIDAndArgsWithTypes(
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mlir::Value cacheHint = thisOp.getL2CacheHint();
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const bool hasCacheHint = static_cast<bool>(cacheHint);
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- llvm::Value *i64Undef =
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- llvm::UndefValue::get(llvm::IntegerType::get(ctx, 64));
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- args.push_back(hasCacheHint ? mt.lookupValue(cacheHint) : i64Undef);
+ llvm::Value *i64Poison =
+ llvm::PoisonValue::get(llvm::IntegerType::get(ctx, 64));
+ args.push_back(hasCacheHint ? mt.lookupValue(cacheHint) : i64Poison);
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args.push_back(builder.getInt1(hasCacheHint));
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llvm::Intrinsic::ID iid;
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