@@ -7,17 +7,15 @@ target triple = "nvptx64-nvidia-cuda"
77define i1 @and_ord (float %a , float %b ) {
88; CHECK-LABEL: and_ord(
99; CHECK: {
10- ; CHECK-NEXT: .reg .pred %p<4 >;
10+ ; CHECK-NEXT: .reg .pred %p<2 >;
1111; CHECK-NEXT: .reg .b32 %r<2>;
1212; CHECK-NEXT: .reg .f32 %f<3>;
1313; CHECK-EMPTY:
1414; CHECK-NEXT: // %bb.0:
1515; CHECK-NEXT: ld.param.f32 %f1, [and_ord_param_0];
16- ; CHECK-NEXT: setp.num.f32 %p1, %f1, %f1;
1716; CHECK-NEXT: ld.param.f32 %f2, [and_ord_param_1];
18- ; CHECK-NEXT: setp.num.f32 %p2, %f2, %f2;
19- ; CHECK-NEXT: and.pred %p3, %p1, %p2;
20- ; CHECK-NEXT: selp.b32 %r1, 1, 0, %p3;
17+ ; CHECK-NEXT: setp.num.f32 %p1, %f1, %f2;
18+ ; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
2119; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
2220; CHECK-NEXT: ret;
2321 %c = fcmp ord float %a , 0 .0
@@ -29,17 +27,15 @@ define i1 @and_ord(float %a, float %b) {
2927define i1 @or_uno (float %a , float %b ) {
3028; CHECK-LABEL: or_uno(
3129; CHECK: {
32- ; CHECK-NEXT: .reg .pred %p<4 >;
30+ ; CHECK-NEXT: .reg .pred %p<2 >;
3331; CHECK-NEXT: .reg .b32 %r<2>;
3432; CHECK-NEXT: .reg .f32 %f<3>;
3533; CHECK-EMPTY:
3634; CHECK-NEXT: // %bb.0:
3735; CHECK-NEXT: ld.param.f32 %f1, [or_uno_param_0];
38- ; CHECK-NEXT: setp.nan.f32 %p1, %f1, %f1;
3936; CHECK-NEXT: ld.param.f32 %f2, [or_uno_param_1];
40- ; CHECK-NEXT: setp.nan.f32 %p2, %f2, %f2;
41- ; CHECK-NEXT: or.pred %p3, %p1, %p2;
42- ; CHECK-NEXT: selp.b32 %r1, 1, 0, %p3;
37+ ; CHECK-NEXT: setp.nan.f32 %p1, %f1, %f2;
38+ ; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
4339; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
4440; CHECK-NEXT: ret;
4541 %c = fcmp uno float %a , 0 .0
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