@@ -680,7 +680,7 @@ def ROCDL_V2BF16Type : FixedVectorOfLengthAndType<[2], [BF16]>,
680680 BuildableType<"::mlir::VectorType::get("
681681 "{2},$_builder.getBF16Type())">;
682682
683- // TODO: The word and byte selectors are immarg in LLVM
683+ // TODO: The word and byte selectors are immarg in LLVM
684684// update to be attributes in MLIR
685685//===---------------------------------------------------------------------===//
686686// 16-bit float intrinsics
@@ -1129,7 +1129,7 @@ def ROCDL_TargetAttr :
11291129 StringRefParameter<"Target chip features.", "\"\"">:$features,
11301130 // Also update the default builder below and rocdl-attach-target in
11311131 // Dialect/GPU/Transforms/Passes.td .
1132- StringRefParameter<"ABI version.", "\"500 \"">:$abi,
1132+ StringRefParameter<"ABI version.", "\"600 \"">:$abi,
11331133 OptionalParameter<"DictionaryAttr", "Target specific flags.">:$flags,
11341134 OptionalParameter<"ArrayAttr", "Files to link to the LLVM module.">:$link
11351135 );
@@ -1141,7 +1141,7 @@ def ROCDL_TargetAttr :
11411141 CArg<"StringRef", "\"amdgcn-amd-amdhsa\"">:$triple,
11421142 CArg<"StringRef", "\"gfx900\"">:$chip,
11431143 CArg<"StringRef", "\"\"">:$features,
1144- CArg<"StringRef", "\"500 \"">:$abiVersion,
1144+ CArg<"StringRef", "\"600 \"">:$abiVersion,
11451145 CArg<"DictionaryAttr", "nullptr">:$targetFlags,
11461146 CArg<"ArrayAttr", "nullptr">:$linkFiles), [{
11471147 return Base::get($_ctxt, optLevel, triple, chip, features, abiVersion,
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