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arsenmarsenm
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RISCV: Implement isLoadFromStackSlot/isStoreToStackSlot for rvv
This partially helps avoid regressions in a future regalloc patch. It isn't sufficient, and I think there are more missing implementations of the copy and spill hooks.
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6 files changed

+35
-23
lines changed

6 files changed

+35
-23
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -118,6 +118,12 @@ Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
118118
case RISCV::FLD:
119119
MemBytes = 8;
120120
break;
121+
case RISCV::VL8RE8_V:
122+
if (!MI.getOperand(1).isFI())
123+
return Register();
124+
FrameIndex = MI.getOperand(1).getIndex();
125+
MemBytes = ~0u;
126+
return MI.getOperand(0).getReg();
121127
}
122128

123129
if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
@@ -158,6 +164,12 @@ Register RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
158164
case RISCV::FSD:
159165
MemBytes = 8;
160166
break;
167+
case RISCV::VS8R_V:
168+
if (!MI.getOperand(1).isFI())
169+
return Register();
170+
FrameIndex = MI.getOperand(1).getIndex();
171+
MemBytes = ~0u;
172+
return MI.getOperand(0).getReg();
161173
}
162174

163175
if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&

‎llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2339,14 +2339,14 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
23392339
; RV32-NEXT: add a4, sp, a4
23402340
; RV32-NEXT: addi a4, a4, 16
23412341
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
2342-
; RV32-NEXT: vsrl.vi v16, v16, 2, v0.t
2342+
; RV32-NEXT: vsrl.vi v8, v16, 2, v0.t
23432343
; RV32-NEXT: csrr a4, vlenb
23442344
; RV32-NEXT: li a5, 48
23452345
; RV32-NEXT: mul a4, a4, a5
23462346
; RV32-NEXT: add a4, sp, a4
23472347
; RV32-NEXT: addi a4, a4, 16
2348-
; RV32-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload
2349-
; RV32-NEXT: vand.vv v16, v16, v8, v0.t
2348+
; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
2349+
; RV32-NEXT: vand.vv v16, v8, v16, v0.t
23502350
; RV32-NEXT: csrr a4, vlenb
23512351
; RV32-NEXT: li a5, 24
23522352
; RV32-NEXT: mul a4, a4, a5

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2292,17 +2292,17 @@ define <32 x i64> @vp_ctlz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
22922292
; RV32-NEXT: addi a0, a0, 48
22932293
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
22942294
; RV32-NEXT: csrr a0, vlenb
2295-
; RV32-NEXT: li a1, 48
2295+
; RV32-NEXT: li a1, 40
22962296
; RV32-NEXT: mul a0, a0, a1
22972297
; RV32-NEXT: add a0, sp, a0
22982298
; RV32-NEXT: addi a0, a0, 48
2299-
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
2299+
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
23002300
; RV32-NEXT: csrr a0, vlenb
2301-
; RV32-NEXT: li a1, 40
2301+
; RV32-NEXT: li a1, 48
23022302
; RV32-NEXT: mul a0, a0, a1
23032303
; RV32-NEXT: add a0, sp, a0
23042304
; RV32-NEXT: addi a0, a0, 48
2305-
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
2305+
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
23062306
; RV32-NEXT: vand.vv v16, v16, v8, v0.t
23072307
; RV32-NEXT: csrr a0, vlenb
23082308
; RV32-NEXT: slli a0, a0, 4
@@ -4998,17 +4998,17 @@ define <32 x i64> @vp_ctlz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
49984998
; RV32-NEXT: addi a0, a0, 48
49994999
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
50005000
; RV32-NEXT: csrr a0, vlenb
5001-
; RV32-NEXT: li a1, 48
5001+
; RV32-NEXT: li a1, 40
50025002
; RV32-NEXT: mul a0, a0, a1
50035003
; RV32-NEXT: add a0, sp, a0
50045004
; RV32-NEXT: addi a0, a0, 48
5005-
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
5005+
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
50065006
; RV32-NEXT: csrr a0, vlenb
5007-
; RV32-NEXT: li a1, 40
5007+
; RV32-NEXT: li a1, 48
50085008
; RV32-NEXT: mul a0, a0, a1
50095009
; RV32-NEXT: add a0, sp, a0
50105010
; RV32-NEXT: addi a0, a0, 48
5011-
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
5011+
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
50125012
; RV32-NEXT: vand.vv v16, v16, v8, v0.t
50135013
; RV32-NEXT: csrr a0, vlenb
50145014
; RV32-NEXT: slli a0, a0, 4

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -343,16 +343,16 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
343343
; RV32-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill
344344
; RV32-NEXT: vmv1r.v v0, v14
345345
; RV32-NEXT: csrr a1, vlenb
346-
; RV32-NEXT: li a3, 72
347-
; RV32-NEXT: mul a1, a1, a3
346+
; RV32-NEXT: slli a1, a1, 6
348347
; RV32-NEXT: add a1, sp, a1
349348
; RV32-NEXT: addi a1, a1, 16
350-
; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
349+
; RV32-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
351350
; RV32-NEXT: csrr a1, vlenb
352-
; RV32-NEXT: slli a1, a1, 6
351+
; RV32-NEXT: li a3, 72
352+
; RV32-NEXT: mul a1, a1, a3
353353
; RV32-NEXT: add a1, sp, a1
354354
; RV32-NEXT: addi a1, a1, 16
355-
; RV32-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
355+
; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
356356
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
357357
; RV32-NEXT: vmerge.vvm v16, v8, v16, v0
358358
; RV32-NEXT: csrr a1, vlenb

‎llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1109,9 +1109,9 @@ define <vscale x 16 x i64> @fshr_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
11091109
; CHECK-NEXT: mul a0, a0, a1
11101110
; CHECK-NEXT: add a0, sp, a0
11111111
; CHECK-NEXT: addi a0, a0, 16
1112-
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
1112+
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
11131113
; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
1114-
; CHECK-NEXT: vand.vx v8, v16, a3, v0.t
1114+
; CHECK-NEXT: vand.vx v8, v8, a3, v0.t
11151115
; CHECK-NEXT: csrr a0, vlenb
11161116
; CHECK-NEXT: slli a0, a0, 4
11171117
; CHECK-NEXT: add a0, sp, a0

‎llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -10357,17 +10357,17 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
1035710357
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
1035810358
; ZVFHMIN-NEXT: csrr a4, vlenb
1035910359
; ZVFHMIN-NEXT: slli a4, a4, 3
10360-
; ZVFHMIN-NEXT: mv a5, a4
10361-
; ZVFHMIN-NEXT: slli a4, a4, 1
10362-
; ZVFHMIN-NEXT: add a4, a4, a5
1036310360
; ZVFHMIN-NEXT: add a4, sp, a4
1036410361
; ZVFHMIN-NEXT: addi a4, a4, 16
10365-
; ZVFHMIN-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
10362+
; ZVFHMIN-NEXT: vl8r.v v24, (a4) # Unknown-size Folded Reload
1036610363
; ZVFHMIN-NEXT: csrr a4, vlenb
1036710364
; ZVFHMIN-NEXT: slli a4, a4, 3
10365+
; ZVFHMIN-NEXT: mv a5, a4
10366+
; ZVFHMIN-NEXT: slli a4, a4, 1
10367+
; ZVFHMIN-NEXT: add a4, a4, a5
1036810368
; ZVFHMIN-NEXT: add a4, sp, a4
1036910369
; ZVFHMIN-NEXT: addi a4, a4, 16
10370-
; ZVFHMIN-NEXT: vl8r.v v24, (a4) # Unknown-size Folded Reload
10370+
; ZVFHMIN-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
1037110371
; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
1037210372
; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
1037310373
; ZVFHMIN-NEXT: csrr a3, vlenb

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