Additional cleanup + format

adam-yang · adam-yang · commit 84d8dd8df6bb · 2025-03-17T20:24:23.000-07:00
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -436,7 +436,7 @@ class TargetRegisterInfo : public MCRegisterInfo {
   /// \returns an empty set if there is no set of covering sub registers.
   std::vector<unsigned>
   getMinimalSpanningSubRegIdxSetForLaneMask(const TargetRegisterClass *RC,
-                                            LaneBitmask mask) const;
+                                            LaneBitmask Mask) const;
 
   /// The lane masks returned by getSubRegIndexLaneMask() above can only be
   /// used to determine if sub-registers overlap - they can't be used to
diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -730,14 +730,14 @@ void TargetRegisterInfo::dumpReg(Register Reg, unsigned SubRegIndex,
 
 std::vector<unsigned>
 TargetRegisterInfo::getMinimalSpanningSubRegIdxSetForLaneMask(
-    const TargetRegisterClass *RC, LaneBitmask mask) const {
+    const TargetRegisterClass *RC, LaneBitmask Mask) const {
   // TODO: this could replace the code it was copied from in SplitKit.cpp
 
   // First pass: Try to find a perfectly matching subregister index.
   // If none exists find the one covering the most lanemask bits.
   SmallVector<unsigned, 8> PossibleIndexes;
   unsigned BestIdx = 0;
-  const LaneBitmask avoid = ~mask;
+  const LaneBitmask Avoid = ~Mask;
   {
     unsigned BestCover = 0;
     for (unsigned Idx = 1, E = getNumSubRegIndices(); Idx < E; ++Idx) {
@@ -746,13 +746,13 @@ TargetRegisterInfo::getMinimalSpanningSubRegIdxSetForLaneMask(
         continue;
       LaneBitmask SubRegMask = getSubRegIndexLaneMask(Idx);
       // Early exit if we found a perfect match.
-      if (SubRegMask == mask) {
+      if (SubRegMask == Mask) {
         BestIdx = Idx;
         break;
       }
 
       // The index must not cover any lanes outside
-      if ((SubRegMask & avoid).any())
+      if ((SubRegMask & Avoid).any())
         continue;
 
       unsigned PopCount = SubRegMask.getNumLanes();
@@ -767,36 +767,36 @@ TargetRegisterInfo::getMinimalSpanningSubRegIdxSetForLaneMask(
   // Abort if we cannot possibly implement the COPY with the given indexes.
   if (BestIdx == 0) {
     LLVM_DEBUG(dbgs() << "Unable to find minimal spanning sub register(s) for "
-                      << getRegClassName(RC) << " mask " << PrintLaneMask(mask)
+                      << getRegClassName(RC) << " mask " << PrintLaneMask(Mask)
                       << '\n');
     assert(false && "Impossible to span reg class");
     return std::vector<unsigned>();
   }
 
-  std::vector<unsigned> result;
-  result.push_back(BestIdx);
+  std::vector<unsigned> Result;
+  Result.push_back(BestIdx);
 
   // Greedy heuristic: Keep iterating keeping the best covering subreg index
   // each time.
-  mask &= ~(getSubRegIndexLaneMask(BestIdx));
-  while (mask.any()) {
+  Mask &= ~(getSubRegIndexLaneMask(BestIdx));
+  while (Mask.any()) {
     BestIdx = 0;
     int BestCover = std::numeric_limits<int>::min();
     for (unsigned Idx : PossibleIndexes) {
       LaneBitmask SubRegMask = getSubRegIndexLaneMask(Idx);
       // Early exit if we found a perfect match.
-      if (SubRegMask == mask) {
+      if (SubRegMask == Mask) {
         BestIdx = Idx;
         break;
       }
 
       // Guaranteed above
-      assert((SubRegMask & avoid).none());
+      assert((SubRegMask & Avoid).none());
 
       // Try to cover as much of the remaining lanes as possible but as few of
       // the already covered lanes as possible.
-      int Cover = (SubRegMask & mask).getNumLanes() -
-                  (SubRegMask & ~mask).getNumLanes();
+      int Cover = (SubRegMask & Mask).getNumLanes() -
+                  (SubRegMask & ~Mask).getNumLanes();
       if (Cover > BestCover) {
         BestCover = Cover;
         BestIdx = Idx;
@@ -805,16 +805,16 @@ TargetRegisterInfo::getMinimalSpanningSubRegIdxSetForLaneMask(
 
     if (BestIdx == 0) {
       LLVM_DEBUG(dbgs() << "Unable to find minimal spanning sub register(s) for "
-                        << getRegClassName(RC) << " mask " << PrintLaneMask(mask)
+                        << getRegClassName(RC) << " mask " << PrintLaneMask(Mask)
                         << '\n');
       assert(false && "Impossible to span reg class");
       return std::vector<unsigned>();
     }
 
-    result.push_back(BestIdx);
-    mask &= ~getSubRegIndexLaneMask(BestIdx);
+    Result.push_back(BestIdx);
+    Mask &= ~getSubRegIndexLaneMask(BestIdx);
   }
 
-  return result;
+  return Result;
 }
 
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUHotBlockRematerialize.cpp b/llvm/lib/Target/AMDGPU/AMDGPUHotBlockRematerialize.cpp
@@ -3287,7 +3287,8 @@ void sortSubExpCandidates(std::vector<SubExp> &SubExpCandidates) {
   MapVector<SubExp *, SortNode> SortMap;
   for (auto It : InputMap) {
     unsigned Reg = It.first;
-    MapVector<Register, SetVector<SubExp *>>::iterator OutIt = OutputMap.find(Reg);
+    MapVector<Register, SetVector<SubExp *>>::iterator OutIt =
+        OutputMap.find(Reg);
     if (OutIt == OutputMap.end())
       continue;
     auto &InExps = It.second;
@@ -3622,8 +3623,7 @@ collectPassThrus(MachineBasicBlock *MBB,
   return PassThrus;
 }
 // Try to build a free subExp which all input is passThrus.
-SubExp buildFreeSubExp(SubExp &Exp,
-                       GCNRPTracker::LiveRegSet &PassThrus,
+SubExp buildFreeSubExp(SubExp &Exp, GCNRPTracker::LiveRegSet &PassThrus,
                        MachineRegisterInfo &MRI, const SIRegisterInfo *SIRI) {
   SubExp FreeExp;
   // Try to split the subExp to find a help case.
@@ -3777,8 +3777,7 @@ std::vector<SubExp> buildSubExpCandidates(
       }
       if (!canHelpPressureWhenSink(Exp, PassThrus, MRI, SIRI, MLI, DT,
                                    IsCanClone, IsSgprBound)) {
-        if (AllowPartialUseInSubExp &&
-            Exp.isSafeToMove(MRI)) {
+        if (AllowPartialUseInSubExp && Exp.isSafeToMove(MRI)) {
           SubExp FreeSubExp = buildFreeSubExp(Exp, PassThrus, MRI, SIRI);
           if (canHelpPressureWhenSink(FreeSubExp, PassThrus, MRI, SIRI, MLI, DT,
                                       IsCanClone, IsSgprBound)) {
@@ -4249,9 +4248,8 @@ bool perBlockPassthruRemat(Remat *Remat, std::vector<HotBlock> &HotBlocks,
       continue;
 
     // Collect pass thru regs.
-    GCNRPTracker::LiveRegSet PassThrus =
-        collectPassThrus(MBB, InputLive, OutputLive,
-                         LiveRegCandidates, MRI, IsCanClone);
+    GCNRPTracker::LiveRegSet PassThrus = collectPassThrus(
+        MBB, InputLive, OutputLive, LiveRegCandidates, MRI, IsCanClone);
 
     // Group pass thru regs by def MBB.
     SmallVector<std::pair<MachineBasicBlock *, GCNRPTracker::LiveRegSet>>
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMIRUtils.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMIRUtils.cpp
@@ -1,3 +1,17 @@
+//===------- AMDGPUMIRUtils.cpp - Helpers for MIR passes ------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+/// \file
+/// \brief Helper functions for MIR passes.
+//
+//===----------------------------------------------------------------------===//
+
 #include "SIInstrInfo.h"
 #include "SIMachineFunctionInfo.h"
 #include "SIRegisterInfo.h"
@@ -383,8 +397,9 @@ struct Piece {
   }
 };
 
-static void updateSubReg(MachineOperand &UseMO, const llvm::TargetRegisterClass *NewRC,
-                  unsigned Offset, const SIRegisterInfo *SIRI) {
+static void updateSubReg(MachineOperand &UseMO,
+                         const llvm::TargetRegisterClass *NewRC,
+                         unsigned Offset, const SIRegisterInfo *SIRI) {
   unsigned Size = NewRC->getLaneMask().getNumLanes();
   if (Size == 1) {
     UseMO.setSubReg(0);
@@ -529,21 +544,23 @@ bool removeUnusedLanes(llvm::MachineInstr &MI, MachineRegisterInfo &MRI,
     case 1:
       return reduceChannel(Piece.Offset, MI,
                            SIII->get(IsImm ? AMDGPU::S_BUFFER_LOAD_DWORD_IMM
-                                          : AMDGPU::S_BUFFER_LOAD_DWORD_SGPR),
+                                           : AMDGPU::S_BUFFER_LOAD_DWORD_SGPR),
                            MRI, SIRI, SIII, SlotIndexes);
     case 2:
       return reduceChannel(Piece.Offset, MI,
-                           SIII->get(IsImm ? AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM
-                                          : AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR),
+                           SIII->get(IsImm
+                                         ? AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM
+                                         : AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR),
                            MRI, SIRI, SIII, SlotIndexes);
     case 3:
       if (FullMask == 0xf)
         return false;
       LLVM_FALLTHROUGH;
     case 4:
       return reduceChannel(Piece.Offset, MI,
-                           SIII->get(IsImm ? AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM
-                                          : AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR),
+                           SIII->get(IsImm
+                                         ? AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM
+                                         : AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR),
                            MRI, SIRI, SIII, SlotIndexes);
     case 5:
     case 6:
@@ -553,8 +570,9 @@ bool removeUnusedLanes(llvm::MachineInstr &MI, MachineRegisterInfo &MRI,
       LLVM_FALLTHROUGH;
     case 8:
       return reduceChannel(Piece.Offset, MI,
-                           SIII->get(IsImm ? AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM
-                                          : AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR),
+                           SIII->get(IsImm
+                                         ? AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM
+                                         : AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR),
                            MRI, SIRI, SIII, SlotIndexes);
     }
 
@@ -751,19 +769,19 @@ unsigned get_reg_size(unsigned Reg, const MachineRegisterInfo &MRI,
 void write_live(unsigned Reg, LaneBitmask Mask, const MachineRegisterInfo &MRI,
                 const SIRegisterInfo *SIRI, raw_ostream &OS) {
   if (Mask.none()) {
-    unsigned size = get_reg_size(Reg, MRI, SIRI);
-    Mask = LaneBitmask((1 << size) - 1);
+    unsigned Size = get_reg_size(Reg, MRI, SIRI);
+    Mask = LaneBitmask((1 << Size) - 1);
   }
-  unsigned mask = Mask.getAsInteger();
+  unsigned IntMask = Mask.getAsInteger();
   for (unsigned i = 0; i <= Mask.getHighestLane(); i++) {
-    if (mask & (1 << i)) {
+    if (IntMask & (1 << i)) {
       write_reg(Reg, i, MRI, SIRI, OS);
       OS << ",\n";
     }
   }
 }
 
-void write_dag_input_node(unsigned ID, unsigned reg, unsigned mask,
+void write_dag_input_node(unsigned ID, unsigned Reg, unsigned Mask,
                           const MachineRegisterInfo &MRI,
                           const SIRegisterInfo *SIRI, raw_ostream &OS) {
   OS << "{";
@@ -773,13 +791,13 @@ void write_dag_input_node(unsigned ID, unsigned reg, unsigned mask,
 
   OS << ",";
 
-  auto WriteReg = [&reg, &MRI, &SIRI, &OS]() { print_reg(reg, MRI, SIRI, OS); };
+  auto WriteReg = [&Reg, &MRI, &SIRI, &OS]() { print_reg(Reg, MRI, SIRI, OS); };
 
   json_pair("reg", WriteReg, OS);
 
   OS << ",";
 
-  auto WriteMask = [&mask, &OS]() { OS << mask; };
+  auto WriteMask = [&Mask, &OS]() { OS << Mask; };
 
   json_pair("mask", WriteMask, OS);
 
@@ -1220,8 +1238,8 @@ void write_file(const MDNode *FileNode, raw_ostream &OS) {
   OS << ",\n";
 
   const MDString *Content = cast<MDString>(FileNode->getOperand(1).get());
-  std::string str = get_legal_str(Content);
-  auto WriteContent = [&str, &OS]() { OS << str; };
+  std::string Str = get_legal_str(Content);
+  auto WriteContent = [&Str, &OS]() { OS << Str; };
   json_pair("content", WriteContent, OS);
   OS << "\n},\n";
 }
@@ -1468,8 +1486,7 @@ void write_function(MachineFunction &MF, LiveIntervals *LIS,
   // Check debug info.
   const Function &F = MF.getFunction();
   const Module *M = F.getParent();
-  const NamedMDNode *SourceMD =
-      M->getNamedMetadata("dx.source.contents");
+  const NamedMDNode *SourceMD = M->getNamedMetadata("dx.source.contents");
   if (SourceMD) {
     write_dbg_info(MF, LIS, MRI, SIII, SIRI, SlotIndexes, SourceMD, OS);
   }
@@ -1530,7 +1547,8 @@ class ContributionList {
 
 void buildMIContribution(MachineInstr &MI,
                          DenseSet<MachineInstr *> &ContributorSet,
-                         DenseSet<MachineInstr *> &ContributedSet, MachineRegisterInfo &MRI) {
+                         DenseSet<MachineInstr *> &ContributedSet,
+                         MachineRegisterInfo &MRI) {
   for (MachineOperand &UseMO : MI.uses()) {
     if (!UseMO.isReg())
       continue;
@@ -1938,8 +1956,7 @@ MachineBasicBlock::iterator llvm::findOrCreateInsertionPointForSccDef(
   //      MI
   //      S_CMP_LG_U32 %SavedSCC, 0       # Restore SCC
   //
-  Register TmpScc =
-      MRI->createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
+  Register TmpScc = MRI->createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
   DebugLoc DL = MI->getDebugLoc();
   BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_CSELECT_B32), TmpScc)
       .addImm(-1)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMIRUtils.h b/llvm/lib/Target/AMDGPU/AMDGPUMIRUtils.h
@@ -1,8 +1,20 @@
+//===------- AMDGPUMIRUtils.h - Helpers for MIR passes --------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+/// \file
+/// \brief Helper functions for MIR passes.
+//
+//===----------------------------------------------------------------------===//
+
 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMIRUTILS_H
 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUMIRUTILS_H
 
-#pragma once
-
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/DenseSet.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
@@ -51,9 +63,9 @@ bool isSub0Sub1SingleDef(unsigned Reg, const llvm::MachineRegisterInfo &MRI);
 
 llvm::LaneBitmask getRegMask(const llvm::MachineOperand &MO,
                              const llvm::MachineRegisterInfo &MRI);
-void andLiveRegSet(LiveSet &targetSet, const LiveSet &inputSet);
-void andNotLiveRegSet(LiveSet &targetSet, const LiveSet &inputSet);
-void mergeLiveRegSet(LiveSet &targetSet, const LiveSet &inputSet);
+void andLiveRegSet(LiveSet &TargetSet, const LiveSet &InputSet);
+void andNotLiveRegSet(LiveSet &TargetSet, const LiveSet &InputSet);
+void mergeLiveRegSet(LiveSet &TargetSet, const LiveSet &InputSet);
 llvm::MachineBasicBlock *split(llvm::MachineInstr *I);
 
 // For inst like S_BUFFER_LOAD_DWORDX16, change to S_BUFFER_LOAD_DWORDX4 if only
@@ -71,9 +83,6 @@ bool reach_block(llvm::MachineBasicBlock *FromBB,
 void viewCFGWithPhi(llvm::MachineFunction &MF);
 void write_contribution_list(llvm::MachineFunction &MF, const char *Filename);
 
-llvm::MachineBasicBlock *createNullExportBlock(llvm::MachineFunction &MF,
-                                               const llvm::SIInstrInfo *TII);
-
 bool getNonDebugMBBEnd(llvm::MachineBasicBlock::reverse_iterator &BBEnd,
                        llvm::MachineBasicBlock &MBB);
 
@@ -128,7 +137,7 @@ llvm::MachineBasicBlock::iterator findOrCreateInsertionPointForSccDef(
 // local.
 bool isLocalLiveInterval(
     const llvm::LiveInterval &LI, llvm::SlotIndexes *Indexes,
-    llvm::SmallDenseSet<llvm::MachineBasicBlock *, 2> &touchedMBBSet);
+    llvm::SmallDenseSet<llvm::MachineBasicBlock *, 2> &TouchedMBBSet);
 bool isLocalLiveInterval(const llvm::LiveInterval &LI,
                          llvm::SlotIndexes *Indexes);
 
@@ -149,13 +158,12 @@ bool isFastMathInst(llvm::MachineInstr &MI);
 
 namespace pressure {
 void print_reg(llvm::Register Reg, const llvm::MachineRegisterInfo &MRI,
-               const llvm::SIRegisterInfo *SIRI, llvm::raw_ostream &os);
+               const llvm::SIRegisterInfo *SIRI, llvm::raw_ostream &OS);
 void write_pressure(llvm::MachineFunction &MF, llvm::LiveIntervals *LIS,
                     const char *Filename);
 void write_pressure(llvm::MachineFunction &MF, llvm::LiveIntervals *LIS,
-                    llvm::raw_ostream &os);
+                    llvm::raw_ostream &OS);
 } // namespace pressure
-// bool IsLdsSpillSupportedForHwStage(xmd::HwStage Stage);
 
 // Look for the successor `Succ` of the given `MBB`.
 // Returns MBB->succ_end() if `Succ` is not a successor of MBB.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubExpDag.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSubExpDag.cpp
