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[MCA] SchedulingInfoView: consider negative ReadAdvanceCycle and AcquireAtCycle
MR #126703: - Negative ReadAdvance cycles can be negative, so add ForwardingDelayCycles to Latency (computeInstrLatency).
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3 files changed

+23
-19
lines changed

3 files changed

+23
-19
lines changed

llvm/include/llvm/MC/MCSchedule.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -402,9 +402,9 @@ struct MCSchedModel {
402402
static unsigned getForwardingDelayCycles(ArrayRef<MCReadAdvanceEntry> Entries,
403403
unsigned WriteResourceIdx = 0);
404404

405-
/// Returns the maximum forwarding delay for maximum write latency.
406-
static unsigned getForwardingDelayCycles(const MCSubtargetInfo &STI,
407-
const MCSchedClassDesc &SCDesc);
405+
/// Returns the bypass delay cycle for the maximum latency write cycle
406+
static unsigned getBypassDelayCycles(const MCSubtargetInfo &STI,
407+
const MCSchedClassDesc &SCDesc);
408408

409409
/// Returns the default initialized model.
410410
static const MCSchedModel Default;

llvm/lib/MC/MCSchedule.cpp

Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -175,38 +175,36 @@ MCSchedModel::getForwardingDelayCycles(ArrayRef<MCReadAdvanceEntry> Entries,
175175
return std::abs(DelayCycles);
176176
}
177177

178-
unsigned
179-
MCSchedModel::getForwardingDelayCycles(const MCSubtargetInfo &STI,
180-
const MCSchedClassDesc &SCDesc) {
178+
unsigned MCSchedModel::getBypassDelayCycles(const MCSubtargetInfo &STI,
179+
const MCSchedClassDesc &SCDesc) {
181180

182181
ArrayRef<MCReadAdvanceEntry> Entries = STI.getReadAdvanceEntries(SCDesc);
183182
if (Entries.empty())
184183
return 0;
185184

186185
unsigned Latency = 0;
187-
unsigned maxLatency = 0;
186+
unsigned MaxLatency = 0;
188187
unsigned WriteResourceID = 0;
189188
unsigned DefEnd = SCDesc.NumWriteLatencyEntries;
190189

191190
for (unsigned DefIdx = 0; DefIdx != DefEnd; ++DefIdx) {
192191
// Lookup the definition's write latency in SubtargetInfo.
193192
const MCWriteLatencyEntry *WLEntry =
194193
STI.getWriteLatencyEntry(&SCDesc, DefIdx);
195-
// Early exit if we found an invalid latency.
196-
// Consider no bypass
194+
unsigned Cycles = (unsigned)WLEntry->Cycles;
195+
// Invalid latency. Consider 0 cycle latency
197196
if (WLEntry->Cycles < 0)
198-
return 0;
199-
maxLatency = std::max(Latency, static_cast<unsigned>(WLEntry->Cycles));
200-
if (maxLatency > Latency) {
197+
Cycles = 0;
198+
if (Cycles > Latency) {
199+
MaxLatency = Cycles;
201200
WriteResourceID = WLEntry->WriteResourceID;
202201
}
203-
Latency = maxLatency;
202+
Latency = MaxLatency;
204203
}
205204

206205
for (const MCReadAdvanceEntry &E : Entries) {
207-
if (E.WriteResourceID == WriteResourceID) {
206+
if (E.WriteResourceID == WriteResourceID)
208207
return E.Cycles;
209-
}
210208
}
211209

212210
llvm_unreachable("WriteResourceID not found in MCReadAdvanceEntry entries");

llvm/tools/llvm-mca/Views/SchedulingInfoView.cpp

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -154,8 +154,12 @@ void SchedulingInfoView::collectData(
154154
IIVDEntry.OpcodeName = (std::string)MCII.getName(Inst.getOpcode());
155155
IIVDEntry.NumMicroOpcodes = SCDesc.NumMicroOps;
156156
IIVDEntry.Latency = MCSchedModel::computeInstrLatency(STI, SCDesc);
157+
// Add extra latency due to delays in the forwarding data paths.
158+
IIVDEntry.Latency += MCSchedModel::getForwardingDelayCycles(
159+
STI.getReadAdvanceEntries(SCDesc));
160+
// Get latency with bypass
157161
IIVDEntry.Bypass =
158-
IIVDEntry.Latency - MCSchedModel::getForwardingDelayCycles(STI, SCDesc);
162+
IIVDEntry.Latency - MCSchedModel::getBypassDelayCycles(STI, SCDesc);
159163
IIVDEntry.Throughput =
160164
1.0 / MCSchedModel::getReciprocalThroughput(STI, SCDesc);
161165
raw_string_ostream TempStream(IIVDEntry.Resources);
@@ -168,10 +172,12 @@ void SchedulingInfoView::collectData(
168172
continue;
169173
const MCProcResourceDesc *MCProc =
170174
SM.getProcResource(Index->ProcResourceIdx);
171-
if (Index->ReleaseAtCycle != 1) {
175+
if (Index->ReleaseAtCycle > 1) {
172176
// Output ReleaseAtCycle between [] if not 1 (default)
173-
TempStream << sep
174-
<< format("%s[%d]", MCProc->Name, Index->ReleaseAtCycle);
177+
// This is to be able to evaluate throughput.
178+
// See getReciprocalThroughput in MCSchedule.cpp
179+
// TODO: report AcquireAtCycle to check this scheduling info.
180+
TempStream << sep << format("%s[%d]", MCProc->Name, Index->ReleaseAtCycle);
175181
} else {
176182
TempStream << sep << format("%s", MCProc->Name);
177183
}

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