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1 parent 917960d commit 85026ecCopy full SHA for 85026ec
llvm/lib/Target/AArch64/AArch64SchedA320.td
@@ -38,7 +38,7 @@ let SchedModel = CortexA320Model in {
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// Cortex-A320 is in-order.
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let BufferSize = 0 in {
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def CortexA320UnitALU : ProcResource<1>; // Int ALU
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- def CortexA320UnitMAC : ProcResource<1>; // Int MAC, 64-bi wide
+ def CortexA320UnitMAC : ProcResource<1>; // Int MAC, 64-bit wide
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def CortexA320UnitDiv : ProcResource<1>; // Int Division, not pipelined
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def CortexA320UnitLdSt : ProcResource<1>; // Load/Store shared pipe
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def CortexA320UnitB : ProcResource<1>; // Branch
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