More Whitespace, Flags Type

Author: lenary

llvm/include/llvm/CodeGen/SDNodeInfo.h

@@ -55,12 +55,14 @@ struct SDTypeConstraint {
   MVT::SimpleValueType VT;
 };
 
+using SDNodeTSFlags = uint32_t;
+
 struct SDNodeDesc {
   uint16_t NumResults;
   int16_t NumOperands;
   uint32_t Properties;
   uint32_t Flags;
-  uint32_t TSFlags;
+  SDNodeTSFlags TSFlags;
   unsigned NameOffset;
   unsigned ConstraintOffset;
   unsigned ConstraintCount;

llvm/lib/Target/RISCV/RISCVInstrInfo.td

@@ -15,7 +15,7 @@
 //===----------------------------------------------------------------------===//
 
 class RVSDNode<string opcode, SDTypeProfile type_profile,
-                list<SDNodeProperty> properties = []>
+               list<SDNodeProperty> properties = []>
     : SDNode<"RISCVISD::" # opcode, type_profile, properties> {
   bit HasPassthruOp = false;
   bit HasMaskOp = false;

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

@@ -3003,9 +3003,10 @@ foreach vti = !listconcat(AllFloatVectors, AllBFloatVectors) in {
 // Matches the semantics of the vid.v instruction, with a mask and VL
 // operand.
 let HasMaskOp = true in
-def riscv_vid_vl : RVSDNode<"VID_VL", SDTypeProfile<1, 2,
-                          [SDTCisVec<0>, SDTCVecEltisVT<1, i1>,
-                           SDTCisSameNumEltsAs<0, 1>, SDTCisVT<2, XLenVT>]>, []>;
+def riscv_vid_vl : RVSDNode<"VID_VL", SDTypeProfile<1, 2, [SDTCisVec<0>,
+                                                           SDTCVecEltisVT<1, i1>,
+                                                           SDTCisSameNumEltsAs<0, 1>,
+                                                           SDTCisVT<2, XLenVT>]>>;
 
 def SDTRVVSlide : SDTypeProfile<1, 6, [
   SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisVT<3, XLenVT>,
@@ -3061,6 +3062,3 @@ defm : VPatSlide1VL_VX<riscv_slide1up_vl, "PseudoVSLIDE1UP">;
 defm : VPatSlide1VL_VF<riscv_fslide1up_vl, "PseudoVFSLIDE1UP">;
 defm : VPatSlide1VL_VX<riscv_slide1down_vl, "PseudoVSLIDE1DOWN">;
 defm : VPatSlide1VL_VF<riscv_fslide1down_vl, "PseudoVFSLIDE1DOWN">;
-
-
-

llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td

@@ -135,17 +135,17 @@ def RI_VEXTRACT : CustomRivosXVI<0b010111, OPMVV, (outs GPR:$rd),
 // XLenVT sign extended from the vector element size.  VEXTRACT does *not*
 // have a VL operand.
 def ri_vextract : RVSDNode<"RI_VEXTRACT",
-                         SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<1>,
-                                              SDTCisInt<2>,
-                                              SDTCisInt<1>]>>;
+                           SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<1>,
+                                                SDTCisInt<2>,
+                                                SDTCisInt<1>]>>;
 
 // RI_VINSERT_VL matches the semantics of ri.vinsert.v.x. It carries a VL operand.
 def ri_vinsert_vl : RVSDNode<"RI_VINSERT_VL",
-                           SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>,
-                                                SDTCisInt<0>,
-                                                SDTCisVT<2, XLenVT>,
-                                                SDTCisVT<3, XLenVT>,
-                                                SDTCisVT<4, XLenVT>]>>;
+                             SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>,
+                                                  SDTCisInt<0>,
+                                                  SDTCisVT<2, XLenVT>,
+                                                  SDTCisVT<3, XLenVT>,
+                                                  SDTCisVT<4, XLenVT>]>>;
 
 let Predicates = [HasVendorXRivosVisni], mayLoad = 0, mayStore = 0,
     hasSideEffects = 0, HasSEWOp = 1 in

llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

@@ -24,15 +24,15 @@ def SDT_StorePair : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>,
                                          SDTCisVT<3, XLenVT>]>;
 
 def th_lwud : RVSDNode<"TH_LWUD", SDT_LoadPair,
-                     [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
+                       [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def th_lwd : RVSDNode<"TH_LWD", SDT_LoadPair,
-                    [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
+                      [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def th_ldd : RVSDNode<"TH_LDD", SDT_LoadPair,
-                    [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
+                      [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def th_swd : RVSDNode<"TH_SWD", SDT_StorePair,
-                    [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
+                      [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 def th_sdd : RVSDNode<"TH_SDD", SDT_StorePair,
-                    [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
+                      [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 
 def ImmThreeAsmOperand : AsmOperandClass {
   let Name = "ImmThree";

llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.h

@@ -18,7 +18,7 @@ namespace llvm {
 
 namespace RISCVISD {
 // RISCVISD Node TSFlags
-enum : unsigned {
+enum : llvm::SDNodeTSFlags {
   HasPassthruOpMask = 1 << 0,
   HasMaskOpMask = 1 << 1,
 };