fixup! fremove M68k from patch

michaelmaitland · michaelmaitland · commit 857380f61bd5 · 2024-11-25T14:30:46.000-08:00
diff --git a/llvm/lib/Target/M68k/M68kRegisterInfo.cpp b/llvm/lib/Target/M68k/M68kRegisterInfo.cpp
@@ -136,7 +136,7 @@ BitVector M68kRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
 
   // Registers reserved by users
   for (size_t Reg = 0, Total = getNumRegs(); Reg != Total; ++Reg) {
-    if (MF.getSubtarget().isRegisterReservedByUser(Reg))
+    if (MF.getSubtarget<M68kSubtarget>().isRegisterReservedByUser(Reg))
       setBitVector(Reg);
   }
 
diff --git a/llvm/lib/Target/M68k/M68kSubtarget.h b/llvm/lib/Target/M68k/M68kSubtarget.h
@@ -107,7 +107,7 @@ class M68kSubtarget : public M68kGenSubtargetInfo {
 
   bool isPositionIndependent() const;
 
-  bool isRegisterReservedByUser(Register R) const override {
+  bool isRegisterReservedByUser(Register R) const {
     assert(R < M68k::NUM_TARGET_REGS && "Register out of range");
     return UserReservedRegister[R];
   }
diff --git a/llvm/test/CodeGen/M68k/fixed-csr.ll b/llvm/test/CodeGen/M68k/fixed-csr.ll

Original file line number	Diff line number	Diff line change
`@@ -136,7 +136,7 @@ BitVector M68kRegisterInfo::getReservedRegs(const MachineFunction &MF) const {`
`136`	`136`
`137`	`137`	`// Registers reserved by users`
`138`	`138`	`for (size_t Reg = 0, Total = getNumRegs(); Reg != Total; ++Reg) {`
`139`		`- if (MF.getSubtarget().isRegisterReservedByUser(Reg))`
	`139`	`+ if (MF.getSubtarget<M68kSubtarget>().isRegisterReservedByUser(Reg))`
`140`	`140`	`setBitVector(Reg);`
`141`	`141`	`}`
`142`	`142`
Original file line number	Diff line number	Diff line change
`@@ -107,7 +107,7 @@ class M68kSubtarget : public M68kGenSubtargetInfo {`
`107`	`107`
`108`	`108`	`bool isPositionIndependent() const;`
`109`	`109`
`110`		`- bool isRegisterReservedByUser(Register R) const override {`
	`110`	`+ bool isRegisterReservedByUser(Register R) const {`
`111`	`111`	`assert(R < M68k::NUM_TARGET_REGS && "Register out of range");`
`112`	`112`	`return UserReservedRegister[R];`
`113`	`113`	`}`