Comments

Author: Pierre-vh

llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp

@@ -590,7 +590,7 @@ class SIGfx12CacheControl : public SIGfx11CacheControl {
   SIGfx12CacheControl(const GCNSubtarget &ST) : SIGfx11CacheControl(ST) {
     // GFX12.0 and GFX12.5 memory models greatly overlap, and in some cases
     // the behavior is the same if assuming GFX12.0 in CU mode.
-    assert(ST.hasGFX1250Insts() ? ST.isCuModeEnabled() : true);
+    assert(!ST.hasGFX1250Insts() || ST.isCuModeEnabled());
   }
 
   bool insertWait(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
@@ -2592,14 +2592,15 @@ bool SIGfx12CacheControl::finalizeStore(MachineInstr &MI, bool Atomic) const {
   const bool IsRMW = (MI.mayLoad() && MI.mayStore());
   bool Changed = false;
 
-  // GFX12.5 only: xcnt wait is needed before flat and global atomics stores/rmw
+  // GFX12.5 only: xcnt wait is needed before flat and global atomics
+  // stores/rmw.
   if (Atomic && ST.requiresWaitXCntBeforeAtomicStores() && TII->isFLAT(MI)) {
     MachineBasicBlock &MBB = *MI.getParent();
     BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(S_WAIT_XCNT_soft)).addImm(0);
     Changed = true;
   }
 
-  // Remaining fixes do not apply to RMWs
+  // Remaining fixes do not apply to RMWs.
   if (IsRMW)
     return Changed;
 

llvm/lib/Target/AMDGPU/SOPInstructions.td

@@ -1658,7 +1658,7 @@ let OtherPredicates = [HasImageInsts] in {
 
 
 let SubtargetPredicate = HasWaitXcnt in {
-  def S_WAIT_XCNT_soft : SOPP_Pseudo<"s_soft_wait_xcnt", (ins s16imm:$simm16), "$simm16">;
+  def S_WAIT_XCNT_soft : SOPP_Pseudo<"", (ins s16imm:$simm16), "$simm16">;
 }
 
 // Represents the point at which a wave must wait for all outstanding direct loads to LDS.