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[AArch64] Disable Xor merging for certain neoverse cores
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‎llvm/lib/Target/AArch64/AArch64Features.td‎

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@@ -897,6 +897,11 @@ def FeatureUseWzrToVecMove : SubtargetFeature<"use-wzr-to-vec-move",
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"UseWzrToVecMove", "true",
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"Move from WZR to insert 0 into vector registers">;
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// On some processors, 2 operand xor use higher throughput paths than 3 operand xor, making
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// it more beneficial to keep them separate.
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def FeatureDisableXorMerge : SubtargetFeature<"disable-xor-merge",
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"DisableXorMerge", "true",
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"Prevent chained XOR instructions from being merged into EOR3">;
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//===----------------------------------------------------------------------===//
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// Architectures.
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//

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

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@@ -436,6 +436,7 @@ def AllowMisalignedMemAccesses
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: Predicate<"!Subtarget->requiresStrictAlign()">;
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def UseWzrToVecMove : Predicate<"Subtarget->useWzrToVecMove()">;
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def AllowXorToEor3Merge : Predicate<"!Subtarget->disableXorMerge()">;
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//===----------------------------------------------------------------------===//
@@ -1817,10 +1818,12 @@ multiclass EOR3_pattern<ValueType Vec128Ty, ValueType Vec64Ty>{
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dsub)>;
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}
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let Predicates = [AllowXorToEor3Merge], AddedComplexity=1 in {
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defm : EOR3_pattern<v16i8, v8i8>;
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defm : EOR3_pattern<v8i16, v4i16>;
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defm : EOR3_pattern<v4i32, v2i32>;
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defm : EOR3_pattern<v2i64, v1i64>;
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}
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class BCAX_pattern<ValueType VecTy>
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: Pat<(xor (VecTy V128:$Vn), (and (VecTy V128:$Vm), (vnot (VecTy V128:$Va)))),

‎llvm/lib/Target/AArch64/AArch64Processors.td‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1081,7 +1081,8 @@ def ProcessorFeatures {
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FeatureCCIDX,
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FeatureDotProd, FeatureFullFP16, FeatureSB, FeatureSSBS, FeatureSVE,
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FeatureComplxNum, FeatureCRC, FeatureFPARMv8, FeatureJS, FeatureLSE,
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FeatureNEON, FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM, FeatureFPAC];
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FeatureNEON, FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM, FeatureFPAC,
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FeatureDisableXorMerge];
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list<SubtargetFeature> NeoverseN3 = [HasV9_2aOps, FeatureETE, FeatureFP16FML,
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FeatureFullFP16, FeatureMTE, FeaturePerfMon,
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FeatureRandGen, FeatureSPE, FeatureSPE_EEF,
@@ -1109,15 +1110,16 @@ def ProcessorFeatures {
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FeatureCCIDX,
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FeatureSHA3, FeatureSM4, FeatureDotProd, FeatureComplxNum,
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FeatureCRC, FeatureJS, FeatureLSE, FeaturePAuth, FeatureRAS,
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FeatureRCPC, FeatureRDM];
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FeatureRCPC, FeatureRDM, FeatureDisableXorMerge];
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list<SubtargetFeature> NeoverseV2 = [HasV9_0aOps, FeatureBF16, FeatureSPE,
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FeaturePerfMon, FeatureETE, FeatureMatMulInt8,
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FeatureNEON, FeatureSVEBitPerm, FeatureFP16FML,
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FeatureMTE, FeatureRandGen,
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FeatureCCIDX,
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FeatureSVE, FeatureSVE2, FeatureSSBS, FeatureFullFP16, FeatureDotProd,
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FeatureComplxNum, FeatureCRC, FeatureFPARMv8, FeatureJS, FeatureLSE,
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FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM, FeatureFPAC];
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FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM, FeatureFPAC,
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FeatureDisableXorMerge];
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list<SubtargetFeature> NeoverseV3 = [HasV9_2aOps, FeatureETE, FeatureFP16FML,
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FeatureFullFP16, FeatureLS64, FeatureMTE,
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FeaturePerfMon, FeatureRandGen, FeatureSPE,

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td‎

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@@ -517,7 +517,9 @@ def AArch64msb_m1 : PatFrags<(ops node:$pred, node:$op1, node:$op2, node:$op3),
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(vselect node:$pred, (sub node:$op3, (AArch64mul_p_oneuse (SVEAllActive), node:$op2, node:$op1)), node:$op1)]>;
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def AArch64eor3 : PatFrags<(ops node:$op1, node:$op2, node:$op3),
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[(int_aarch64_sve_eor3 node:$op1, node:$op2, node:$op3),
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(xor node:$op1, (xor node:$op2, node:$op3))]>;
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(xor node:$op1, (xor node:$op2, node:$op3))], [{
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return N->getOpcode() != ISD::XOR || !Subtarget->disableXorMerge();
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}]>;
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def AArch64bcax : PatFrags<(ops node:$op1, node:$op2, node:$op3),
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[(int_aarch64_sve_bcax node:$op1, node:$op2, node:$op3),
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(xor node:$op1, (and node:$op2, (vnot node:$op3)))]>;

‎llvm/test/CodeGen/AArch64/eor3-merge.ll‎

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@@ -0,0 +1,26 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --extra_scrub
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; RUN: llc -mtriple=aarch64 -mattr=+sha3,+sve2 -mcpu=neoverse-v1 < %s | FileCheck --check-prefix=CHECK-NOMERGE %s
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; RUN: llc -mtriple=aarch64 -mattr=+sha3,+sve2 -mcpu=neoverse-v2 < %s | FileCheck --check-prefix=CHECK-NOMERGE %s
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; RUN: llc -mtriple=aarch64 -mattr=+sha3,+sve2 -mcpu=neoverse-v3 < %s | FileCheck --check-prefix=CHECK-MERGE %s
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; RUN: llc -mtriple=aarch64 -mattr=+sha3,+sve2 -mcpu=neoverse-n2 < %s | FileCheck --check-prefix=CHECK-NOMERGE %s
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; RUN: llc -mtriple=aarch64 -mattr=+sha3,+sve2 -mcpu=neoverse-n3 < %s | FileCheck --check-prefix=CHECK-MERGE %s
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define <8 x i8> @eor3_8x8(<8 x i8> %0, <8 x i8> %1, <8 x i8> %2) {
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; CHECK-NOMERGE-LABEL: eor3_8x8:
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; CHECK-NOMERGE: // %bb.0:
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; CHECK-NOMERGE-NEXT: eor v1.8b, v1.8b, v2.8b
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; CHECK-NOMERGE-NEXT: eor v0.8b, v1.8b, v0.8b
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; CHECK-NOMERGE-NEXT: ret
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;
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; CHECK-MERGE-LABEL: eor3_8x8:
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; CHECK-MERGE: // %bb.0:
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; CHECK-MERGE-NEXT: // kill: def $d2 killed $d2 def $q2
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; CHECK-MERGE-NEXT: // kill: def $d1 killed $d1 def $q1
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; CHECK-MERGE-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-MERGE-NEXT: eor3 v0.16b, v1.16b, v2.16b, v0.16b
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; CHECK-MERGE-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-MERGE-NEXT: ret
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%4 = xor <8 x i8> %1, %2
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%5 = xor <8 x i8> %4, %0
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ret <8 x i8> %5
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}

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