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[ELF] Pass Ctx & to Symbol::getVA
1 parent 4a011ac commit 861bd36

22 files changed

+125
-121
lines changed

‎lld/ELF/AArch64ErrataFix.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -417,7 +417,7 @@ void Patch843419Section::writeTo(uint8_t *buf) {
417417

418418
// Return address is the next instruction after the one we have just copied.
419419
uint64_t s = getLDSTAddr() + 4;
420-
uint64_t p = patchSym->getVA() + 4;
420+
uint64_t p = patchSym->getVA(ctx) + 4;
421421
ctx.target->relocateNoSym(buf + 4, R_AARCH64_JUMP26, s - p);
422422
}
423423

‎lld/ELF/ARMErrataFix.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -218,7 +218,7 @@ static bool branchDestInFirstRegion(Ctx &ctx, const InputSection *isec,
218218
// or the PLT.
219219
if (r) {
220220
uint64_t dst =
221-
(r->expr == R_PLT_PC) ? r->sym->getPltVA(ctx) : r->sym->getVA();
221+
r->expr == R_PLT_PC ? r->sym->getPltVA(ctx) : r->sym->getVA(ctx);
222222
// Account for Thumb PC bias, usually cancelled to 0 by addend of -4.
223223
destAddr = dst + r->addend + 4;
224224
} else {
@@ -449,7 +449,7 @@ static void implementPatch(ScanResult sr, InputSection *isec,
449449
// Thunk from the patch to the target.
450450
uint64_t dstSymAddr = (sr.rel->expr == R_PLT_PC)
451451
? sr.rel->sym->getPltVA(ctx)
452-
: sr.rel->sym->getVA();
452+
: sr.rel->sym->getVA(ctx);
453453
destIsARM = (dstSymAddr & 1) == 0;
454454
}
455455
psec = make<Patch657417Section>(ctx, isec, sr.off, sr.instr, destIsARM);

‎lld/ELF/Arch/AArch64.cpp‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -360,7 +360,7 @@ void AArch64::writeGotPlt(uint8_t *buf, const Symbol &) const {
360360

361361
void AArch64::writeIgotPlt(uint8_t *buf, const Symbol &s) const {
362362
if (ctx.arg.writeAddends)
363-
write64(ctx, buf, s.getVA());
363+
write64(ctx, buf, s.getVA(ctx));
364364
}
365365

366366
void AArch64::writePltHeader(uint8_t *buf) const {
@@ -416,7 +416,7 @@ bool AArch64::needsThunk(RelExpr expr, RelType type, const InputFile *file,
416416
if (type != R_AARCH64_CALL26 && type != R_AARCH64_JUMP26 &&
417417
type != R_AARCH64_PLT32)
418418
return false;
419-
uint64_t dst = expr == R_PLT_PC ? s.getPltVA(ctx) : s.getVA(a);
419+
uint64_t dst = expr == R_PLT_PC ? s.getPltVA(ctx) : s.getVA(ctx, a);
420420
return !inBranchRange(type, branchAddr, dst);
421421
}
422422

@@ -808,7 +808,7 @@ bool AArch64Relaxer::tryRelaxAdrpAdd(const Relocation &adrpRel,
808808

809809
Symbol &sym = *adrpRel.sym;
810810
// Check if the address difference is within 1MiB range.
811-
int64_t val = sym.getVA() - (secAddr + addRel.offset);
811+
int64_t val = sym.getVA(ctx) - (secAddr + addRel.offset);
812812
if (val < -1024 * 1024 || val >= 1024 * 1024)
813813
return false;
814814

@@ -874,7 +874,7 @@ bool AArch64Relaxer::tryRelaxAdrpLdr(const Relocation &adrpRel,
874874
return false;
875875
// Check if the address difference is within 4GB range.
876876
int64_t val =
877-
getAArch64Page(sym.getVA()) - getAArch64Page(secAddr + adrpRel.offset);
877+
getAArch64Page(sym.getVA(ctx)) - getAArch64Page(secAddr + adrpRel.offset);
878878
if (val != llvm::SignExtend64(val, 33))
879879
return false;
880880

@@ -890,11 +890,11 @@ bool AArch64Relaxer::tryRelaxAdrpLdr(const Relocation &adrpRel,
890890

891891
ctx.target->relocate(
892892
buf + adrpSymRel.offset, adrpSymRel,
893-
SignExtend64(getAArch64Page(sym.getVA()) -
893+
SignExtend64(getAArch64Page(sym.getVA(ctx)) -
894894
getAArch64Page(secAddr + adrpSymRel.offset),
895895
64));
896896
ctx.target->relocate(buf + addRel.offset, addRel,
897-
SignExtend64(sym.getVA(), 64));
897+
SignExtend64(sym.getVA(ctx), 64));
898898
tryRelaxAdrpAdd(adrpSymRel, addRel, secAddr, buf);
899899
return true;
900900
}

‎lld/ELF/Arch/ARM.cpp‎

Lines changed: 12 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -213,7 +213,7 @@ void ARM::writeGotPlt(uint8_t *buf, const Symbol &) const {
213213

214214
void ARM::writeIgotPlt(uint8_t *buf, const Symbol &s) const {
215215
// An ARM entry is the address of the ifunc resolver function.
216-
write32(ctx, buf, s.getVA());
216+
write32(ctx, buf, s.getVA(ctx));
217217
}
218218

219219
// Long form PLT Header that does not have any restrictions on the displacement
@@ -404,26 +404,26 @@ bool ARM::needsThunk(RelExpr expr, RelType type, const InputFile *file,
404404
// Otherwise we need to interwork if STT_FUNC Symbol has bit 0 set (Thumb).
405405
assert(!useThumbPLTs(ctx) &&
406406
"If the source is ARM, we should not need Thumb PLTs");
407-
if (s.isFunc() && expr == R_PC && (s.getVA() & 1))
407+
if (s.isFunc() && expr == R_PC && (s.getVA(ctx) & 1))
408408
return true;
409409
[[fallthrough]];
410410
case R_ARM_CALL: {
411-
uint64_t dst = (expr == R_PLT_PC) ? s.getPltVA(ctx) : s.getVA();
411+
uint64_t dst = (expr == R_PLT_PC) ? s.getPltVA(ctx) : s.getVA(ctx);
412412
return !inBranchRange(type, branchAddr, dst + a) ||
413-
(!ctx.arg.armHasBlx && (s.getVA() & 1));
413+
(!ctx.arg.armHasBlx && (s.getVA(ctx) & 1));
414414
}
415415
case R_ARM_THM_JUMP19:
416416
case R_ARM_THM_JUMP24:
417417
// Source is Thumb, when all PLT entries are ARM interworking is required.
418418
// Otherwise we need to interwork if STT_FUNC Symbol has bit 0 clear (ARM).
419419
if ((expr == R_PLT_PC && !useThumbPLTs(ctx)) ||
420-
(s.isFunc() && (s.getVA() & 1) == 0))
420+
(s.isFunc() && (s.getVA(ctx) & 1) == 0))
421421
return true;
422422
[[fallthrough]];
423423
case R_ARM_THM_CALL: {
424-
uint64_t dst = (expr == R_PLT_PC) ? s.getPltVA(ctx) : s.getVA();
424+
uint64_t dst = (expr == R_PLT_PC) ? s.getPltVA(ctx) : s.getVA(ctx);
425425
return !inBranchRange(type, branchAddr, dst + a) ||
426-
(!ctx.arg.armHasBlx && (s.getVA() & 1) == 0);;
426+
(!ctx.arg.armHasBlx && (s.getVA(ctx) & 1) == 0);
427427
}
428428
}
429429
return false;
@@ -1399,7 +1399,7 @@ void ArmCmseSGSection::writeTo(uint8_t *buf) {
13991399
write16(ctx, p + 4, 0xf000); // B.W S
14001400
write16(ctx, p + 6, 0xb000);
14011401
ctx.target->relocateNoSym(p + 4, R_ARM_THM_JUMP24,
1402-
s->acleSeSym->getVA() -
1402+
s->acleSeSym->getVA(ctx) -
14031403
(getVA() + s->offset + s->size));
14041404
}
14051405
}
@@ -1466,16 +1466,15 @@ template <typename ELFT> void elf::writeARMCmseImportLib(Ctx &ctx) {
14661466
osIsPairs.emplace_back(make<OutputSection>(ctx, shstrtab->name, 0, 0),
14671467
shstrtab);
14681468

1469-
std::sort(ctx.symtab->cmseSymMap.begin(), ctx.symtab->cmseSymMap.end(),
1470-
[](const auto &a, const auto &b) -> bool {
1471-
return a.second.sym->getVA() < b.second.sym->getVA();
1472-
});
1469+
llvm::sort(ctx.symtab->cmseSymMap, [&](const auto &a, const auto &b) {
1470+
return a.second.sym->getVA(ctx) < b.second.sym->getVA(ctx);
1471+
});
14731472
// Copy the secure gateway entry symbols to the import library symbol table.
14741473
for (auto &p : ctx.symtab->cmseSymMap) {
14751474
Defined *d = cast<Defined>(p.second.sym);
14761475
impSymTab->addSymbol(makeDefined(
14771476
ctx, ctx.internalFile, d->getName(), d->computeBinding(ctx),
1478-
/*stOther=*/0, STT_FUNC, d->getVA(), d->getSize(), nullptr));
1477+
/*stOther=*/0, STT_FUNC, d->getVA(ctx), d->getSize(), nullptr));
14791478
}
14801479

14811480
size_t idx = 0;

‎lld/ELF/Arch/AVR.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -110,7 +110,7 @@ bool AVR::needsThunk(RelExpr expr, RelType type, const InputFile *file,
110110
case R_AVR_HI8_LDI_GS:
111111
// A thunk is needed if the symbol's virtual address is out of range
112112
// [0, 0x1ffff].
113-
return s.getVA() >= 0x20000;
113+
return s.getVA(ctx) >= 0x20000;
114114
default:
115115
return false;
116116
}

‎lld/ELF/Arch/LoongArch.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -316,9 +316,9 @@ void LoongArch::writeGotPlt(uint8_t *buf, const Symbol &s) const {
316316
void LoongArch::writeIgotPlt(uint8_t *buf, const Symbol &s) const {
317317
if (ctx.arg.writeAddends) {
318318
if (ctx.arg.is64)
319-
write64le(buf, s.getVA());
319+
write64le(buf, s.getVA(ctx));
320320
else
321-
write32le(buf, s.getVA());
321+
write32le(buf, s.getVA(ctx));
322322
}
323323
}
324324

‎lld/ELF/Arch/Mips.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -96,7 +96,7 @@ RelExpr MIPS<ELFT>::getRelExpr(RelType type, const Symbol &s,
9696
// If the target symbol is not preemptible and is not microMIPS,
9797
// it might be possible to replace jalr/jr instruction by bal/b.
9898
// It depends on the target symbol's offset.
99-
if (!s.isPreemptible && !(s.getVA() & 0x1))
99+
if (!s.isPreemptible && !(s.getVA(ctx) & 0x1))
100100
return R_PC;
101101
return R_NONE;
102102
case R_MICROMIPS_JALR:

‎lld/ELF/Arch/PPC.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -209,7 +209,7 @@ bool PPC::needsThunk(RelExpr expr, RelType type, const InputFile *file,
209209
return true;
210210
if (s.isUndefWeak())
211211
return false;
212-
return !PPC::inBranchRange(type, branchAddr, s.getVA(a));
212+
return !PPC::inBranchRange(type, branchAddr, s.getVA(ctx, a));
213213
}
214214

215215
uint32_t PPC::getThunkSectionSpacing() const { return 0x2000000; }

‎lld/ELF/Arch/PPC64.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -404,7 +404,7 @@ static bool tryRelaxPPC64TocIndirection(Ctx &ctx, const Relocation &rel,
404404
assert(!d->isGnuIFunc());
405405

406406
// Two instructions can materialize a 32-bit signed offset from the toc base.
407-
uint64_t tocRelative = d->getVA(addend) - getPPC64TocBase(ctx);
407+
uint64_t tocRelative = d->getVA(ctx, addend) - getPPC64TocBase(ctx);
408408
if (!isInt<32>(tocRelative))
409409
return false;
410410

@@ -1452,7 +1452,7 @@ bool PPC64::needsThunk(RelExpr expr, RelType type, const InputFile *file,
14521452
// a range-extending thunk.
14531453
// See the comment in getRelocTargetVA() about R_PPC64_CALL.
14541454
return !inBranchRange(type, branchAddr,
1455-
s.getVA(a) +
1455+
s.getVA(ctx, a) +
14561456
getPPC64GlobalEntryToLocalEntryOffset(s.stOther));
14571457
}
14581458

‎lld/ELF/Arch/RISCV.cpp‎

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -214,9 +214,9 @@ void RISCV::writeGotPlt(uint8_t *buf, const Symbol &s) const {
214214
void RISCV::writeIgotPlt(uint8_t *buf, const Symbol &s) const {
215215
if (ctx.arg.writeAddends) {
216216
if (ctx.arg.is64)
217-
write64le(buf, s.getVA());
217+
write64le(buf, s.getVA(ctx));
218218
else
219-
write32le(buf, s.getVA());
219+
write32le(buf, s.getVA(ctx));
220220
}
221221
}
222222

@@ -466,7 +466,7 @@ void RISCV::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
466466
case INTERNAL_R_RISCV_GPREL_I:
467467
case INTERNAL_R_RISCV_GPREL_S: {
468468
Defined *gp = ctx.sym.riscvGlobalPointer;
469-
int64_t displace = SignExtend64(val - gp->getVA(), bits);
469+
int64_t displace = SignExtend64(val - gp->getVA(ctx), bits);
470470
checkInt(ctx, loc, displace, 12, rel);
471471
uint32_t insn = (read32le(loc) & ~(31 << 15)) | (X_GP << 15);
472472
if (rel.type == INTERNAL_R_RISCV_GPREL_I)
@@ -657,7 +657,8 @@ void RISCV::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const {
657657
const Relocation &rel1 = relocs[i + 1];
658658
if (rel.type == R_RISCV_SET_ULEB128 &&
659659
rel1.type == R_RISCV_SUB_ULEB128 && rel.offset == rel1.offset) {
660-
auto val = rel.sym->getVA(rel.addend) - rel1.sym->getVA(rel1.addend);
660+
auto val = rel.sym->getVA(ctx, rel.addend) -
661+
rel1.sym->getVA(ctx, rel1.addend);
661662
if (overwriteULEB128(loc, val) >= 0x80)
662663
errorOrWarn(sec.getLocation(rel.offset) + ": ULEB128 value " +
663664
Twine(val) + " exceeds available space; references '" +
@@ -737,7 +738,7 @@ static void relaxCall(Ctx &ctx, const InputSection &sec, size_t i, uint64_t loc,
737738
const uint64_t insnPair = read64le(sec.content().data() + r.offset);
738739
const uint32_t rd = extractBits(insnPair, 32 + 11, 32 + 7);
739740
const uint64_t dest =
740-
(r.expr == R_PLT_PC ? sym.getPltVA(ctx) : sym.getVA()) + r.addend;
741+
(r.expr == R_PLT_PC ? sym.getPltVA(ctx) : sym.getVA(ctx)) + r.addend;
741742
const int64_t displace = dest - loc;
742743

743744
if (rvc && isInt<12>(displace) && rd == 0) {
@@ -759,7 +760,7 @@ static void relaxCall(Ctx &ctx, const InputSection &sec, size_t i, uint64_t loc,
759760
// Relax local-exec TLS when hi20 is zero.
760761
static void relaxTlsLe(const InputSection &sec, size_t i, uint64_t loc,
761762
Relocation &r, uint32_t &remove) {
762-
uint64_t val = r.sym->getVA(r.addend);
763+
uint64_t val = r.sym->getVA(ctx, r.addend);
763764
if (hi20(val) != 0)
764765
return;
765766
uint32_t insn = read32le(sec.content().data() + r.offset);
@@ -791,7 +792,7 @@ static void relaxHi20Lo12(Ctx &ctx, const InputSection &sec, size_t i,
791792
if (!gp)
792793
return;
793794

794-
if (!isInt<12>(r.sym->getVA(r.addend) - gp->getVA()))
795+
if (!isInt<12>(r.sym->getVA(ctx, r.addend) - gp->getVA(ctx)))
795796
return;
796797

797798
switch (r.type) {
@@ -863,7 +864,7 @@ static bool relax(Ctx &ctx, InputSection &sec) {
863864
// For TLSDESC=>LE, we can use the short form if hi20 is zero.
864865
tlsdescRelax = relaxable(relocs, i);
865866
toLeShortForm = tlsdescRelax && r.expr == R_RELAX_TLS_GD_TO_LE &&
866-
!hi20(r.sym->getVA(r.addend));
867+
!hi20(r.sym->getVA(ctx, r.addend));
867868
[[fallthrough]];
868869
case R_RISCV_TLSDESC_LOAD_LO12:
869870
// For TLSDESC=>LE/IE, AUIPC and L[DW] are removed if relaxable.

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