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[AMDGPU] Add argument range annotations to intrinsics where applicable (#170958)
This commit adds annotations to AMDGPU intrinscis that take arguments which are documented to lie within a specified range, ensuring that invalid instances of these intrinsics don't pass verification. (Note that certain intrinsics that could have range annothations don't, as their existing behavior is to clamp out-of-range values silently.) Disclaimer: tests generated by LLM (code is mine)
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‎llvm/include/llvm/IR/IntrinsicsAMDGPU.td‎

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -653,19 +653,20 @@ def int_amdgcn_cvt_pk_bf8_f16
653653
// byte_sel selects byte to write in vdst.
654654
def int_amdgcn_cvt_sr_fp8_f16 : DefaultAttrsIntrinsic<
655655
[llvm_i32_ty], [llvm_half_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
656-
[IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<3>>]
656+
[IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<3>>, Range<ArgIndex<3>, 0, 4>]
657657
>, ClangBuiltin<"__builtin_amdgcn_cvt_sr_fp8_f16">;
658658

659659
// llvm.amdgcn.cvt.sr.bf8.f16 i32 vdst, half src, i32 seed, i32 old, imm byte_sel [0..3]
660660
// byte_sel selects byte to write in vdst.
661661
def int_amdgcn_cvt_sr_bf8_f16 : DefaultAttrsIntrinsic<
662662
[llvm_i32_ty], [llvm_half_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
663-
[IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<3>>]
663+
[IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<3>>, Range<ArgIndex<3>, 0, 4>]
664664
>, ClangBuiltin<"__builtin_amdgcn_cvt_sr_bf8_f16">;
665665

666666
// llvm.amdgcn.cvt.scale.pk32.f16.bf6 v32f16 vdst, v6i32 src0, i32 scale_sel [0..15]
667667
class AMDGPUCvtScaleIntrinsic<LLVMType DstTy, LLVMType Src0Ty, string name> : DefaultAttrsIntrinsic<
668-
[DstTy], [Src0Ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<2>>]
668+
[DstTy], [Src0Ty, llvm_i32_ty, llvm_i32_ty],
669+
[IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<2>>, Range<ArgIndex<2>, 0, 16>]
669670
>, ClangBuiltin<"__builtin_amdgcn_"#name>;
670671

671672
class AMDGPUCvtScaleF32Intrinsic<LLVMType DstTy, LLVMType Src0Ty, string name> : DefaultAttrsIntrinsic<
@@ -746,7 +747,8 @@ class AMDGPUCvtScaleFP4FP8BF8ToF1632Intrinsic<LLVMType DstTy, string name> : Def
746747
[llvm_i32_ty, // src
747748
llvm_float_ty, // scale
748749
llvm_i32_ty], // src_sel index [0..3]
749-
[IntrNoMem, ImmArg<ArgIndex<2>>]
750+
[IntrNoMem,
751+
ImmArg<ArgIndex<2>>, Range<ArgIndex<2>, 0, 4>]
750752
>, ClangBuiltin<"__builtin_amdgcn_"#name>;
751753

752754
class AMDGPUCvtScale_pk_FromFP8BF8Intrinsic<LLVMType DstTy, string name> : DefaultAttrsIntrinsic<
@@ -783,7 +785,7 @@ class AMDGPUCvtScaleFP8BF8ToF16TiedInputIntrinsic<LLVMType DstTy, string name> :
783785
llvm_float_ty, // scale
784786
llvm_i32_ty, // src_sel_index[0..3]
785787
llvm_i1_ty], // dst_lo_hi_sel[true false]
786-
[IntrNoMem, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>]
788+
[IntrNoMem, ImmArg<ArgIndex<3>>, Range<ArgIndex<3>, 0, 4>, ImmArg<ArgIndex<4>>]
787789
>, ClangBuiltin<"__builtin_amdgcn_"#name>;
788790

789791
class AMDGPUCvtScaleF32ToFP4Intrinsic<string name> : DefaultAttrsIntrinsic<
@@ -793,7 +795,7 @@ class AMDGPUCvtScaleF32ToFP4Intrinsic<string name> : DefaultAttrsIntrinsic<
793795
llvm_float_ty, // src1
794796
llvm_float_ty, // scale
795797
llvm_i32_ty], // dst_sel_index[0..3]
796-
[IntrNoMem, ImmArg<ArgIndex<4>>]
798+
[IntrNoMem, ImmArg<ArgIndex<4>>, Range<ArgIndex<4>, 0, 4>]
797799
>, ClangBuiltin<"__builtin_amdgcn_"#name>;
798800

799801
class AMDGPUCvtScaleF16ToFP4TiedInputIntrinsic<LLVMType SrcTy, string name> : DefaultAttrsIntrinsic<
@@ -802,7 +804,7 @@ class AMDGPUCvtScaleF16ToFP4TiedInputIntrinsic<LLVMType SrcTy, string name> : De
802804
SrcTy, // src
803805
llvm_float_ty, // scale
804806
llvm_i32_ty], // dest_sel_index [0..3]
805-
[IntrNoMem, ImmArg<ArgIndex<3>>]
807+
[IntrNoMem, ImmArg<ArgIndex<3>>, Range<ArgIndex<3>, 0, 4>]
806808
>, ClangBuiltin<"__builtin_amdgcn_"#name>;
807809

808810
class AMDGPUCvtScaleBF16F16F32SRToFP4BF8F8TiedInputIntrinsic<LLVMType Src0Ty, string name> : DefaultAttrsIntrinsic<
@@ -812,7 +814,7 @@ class AMDGPUCvtScaleBF16F16F32SRToFP4BF8F8TiedInputIntrinsic<LLVMType Src0Ty, st
812814
llvm_i32_ty, // seed
813815
llvm_float_ty, // scale
814816
llvm_i32_ty], // dst_sel_index[0..3]
815-
[IntrNoMem, ImmArg<ArgIndex<4>>]
817+
[IntrNoMem, ImmArg<ArgIndex<4>>, Range<ArgIndex<4>, 0, 4>]
816818
>, ClangBuiltin<"__builtin_amdgcn_"#name>;
817819

818820
class AMDGPUCvtScaleSRF32ToBF16F16TiedInputIntrinsic<LLVMType DstTy, string name> : DefaultAttrsIntrinsic<

‎llvm/test/Verifier/AMDGPU/test-cvt-fp4f6f8-immarg-ranges.ll‎

Lines changed: 147 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,147 @@
1+
; RUN: not llvm-as %s -disable-output 2>&1 | FileCheck %s
2+
3+
; --------------------------------------------------------------------
4+
; llvm.amdgcn.cvt.sr.fp8.f16 - byte_sel out of range
5+
; --------------------------------------------------------------------
6+
7+
; CHECK: immarg value 4 out of range [0, 4)
8+
; CHECK-NEXT: %result = call i32 @llvm.amdgcn.cvt.sr.fp8.f16(half %src, i32 %seed, i32 %old, i32 4)
9+
define i32 @test_cvt_sr_fp8_f16_byte_sel_out_of_range(half %src, i32 %seed, i32 %old) {
10+
%result = call i32 @llvm.amdgcn.cvt.sr.fp8.f16(half %src, i32 %seed, i32 %old, i32 4)
11+
ret i32 %result
12+
}
13+
14+
; CHECK: immarg value 10 out of range [0, 4)
15+
; CHECK-NEXT: %result = call i32 @llvm.amdgcn.cvt.sr.fp8.f16(half %src, i32 %seed, i32 %old, i32 10)
16+
define i32 @test_cvt_sr_fp8_f16_byte_sel_way_out_of_range(half %src, i32 %seed, i32 %old) {
17+
%result = call i32 @llvm.amdgcn.cvt.sr.fp8.f16(half %src, i32 %seed, i32 %old, i32 10)
18+
ret i32 %result
19+
}
20+
21+
; --------------------------------------------------------------------
22+
; llvm.amdgcn.cvt.sr.bf8.f16 - byte_sel out of range
23+
; --------------------------------------------------------------------
24+
25+
; CHECK: immarg value 4 out of range [0, 4)
26+
; CHECK-NEXT: %result = call i32 @llvm.amdgcn.cvt.sr.bf8.f16(half %src, i32 %seed, i32 %old, i32 4)
27+
define i32 @test_cvt_sr_bf8_f16_byte_sel_out_of_range(half %src, i32 %seed, i32 %old) {
28+
%result = call i32 @llvm.amdgcn.cvt.sr.bf8.f16(half %src, i32 %seed, i32 %old, i32 4)
29+
ret i32 %result
30+
}
31+
32+
; --------------------------------------------------------------------
33+
; llvm.amdgcn.cvt.scale.pk8.f16.fp8 - scale_sel out of range
34+
; --------------------------------------------------------------------
35+
36+
; CHECK: immarg value 16 out of range [0, 16)
37+
; CHECK-NEXT: %result = call <8 x half> @llvm.amdgcn.cvt.scale.pk8.f16.fp8(<2 x i32> %src, i32 0, i32 16)
38+
define <8 x half> @test_cvt_scale_pk8_f16_fp8_scale_sel_out_of_range(<2 x i32> %src) {
39+
%result = call <8 x half> @llvm.amdgcn.cvt.scale.pk8.f16.fp8(<2 x i32> %src, i32 0, i32 16)
40+
ret <8 x half> %result
41+
}
42+
43+
; CHECK: immarg value 100 out of range [0, 16)
44+
; CHECK-NEXT: %result = call <8 x half> @llvm.amdgcn.cvt.scale.pk8.f16.fp8(<2 x i32> %src, i32 0, i32 100)
45+
define <8 x half> @test_cvt_scale_pk8_f16_fp8_scale_sel_way_out_of_range(<2 x i32> %src) {
46+
%result = call <8 x half> @llvm.amdgcn.cvt.scale.pk8.f16.fp8(<2 x i32> %src, i32 0, i32 100)
47+
ret <8 x half> %result
48+
}
49+
50+
; --------------------------------------------------------------------
51+
; llvm.amdgcn.cvt.scalef32.f32.fp8 - src_sel out of range
52+
; --------------------------------------------------------------------
53+
54+
; CHECK: immarg value 4 out of range [0, 4)
55+
; CHECK-NEXT: %result = call float @llvm.amdgcn.cvt.scalef32.f32.fp8(i32 %src, float %scale, i32 4)
56+
define float @test_cvt_scalef32_f32_fp8_src_sel_out_of_range(i32 %src, float %scale) {
57+
%result = call float @llvm.amdgcn.cvt.scalef32.f32.fp8(i32 %src, float %scale, i32 4)
58+
ret float %result
59+
}
60+
61+
; CHECK: immarg value 7 out of range [0, 4)
62+
; CHECK-NEXT: %result = call float @llvm.amdgcn.cvt.scalef32.f32.fp8(i32 %src, float %scale, i32 7)
63+
define float @test_cvt_scalef32_f32_fp8_src_sel_way_out_of_range(i32 %src, float %scale) {
64+
%result = call float @llvm.amdgcn.cvt.scalef32.f32.fp8(i32 %src, float %scale, i32 7)
65+
ret float %result
66+
}
67+
68+
; --------------------------------------------------------------------
69+
; llvm.amdgcn.cvt.scalef32.f16.fp8 - src_sel_index out of range
70+
; --------------------------------------------------------------------
71+
72+
; CHECK: immarg value 4 out of range [0, 4)
73+
; CHECK-NEXT: %result = call <2 x half> @llvm.amdgcn.cvt.scalef32.f16.fp8(<2 x half> %old, i32 %src, float %scale, i32 4, i1 false)
74+
define <2 x half> @test_cvt_scalef32_f16_fp8_src_sel_index_out_of_range(<2 x half> %old, i32 %src, float %scale) {
75+
%result = call <2 x half> @llvm.amdgcn.cvt.scalef32.f16.fp8(<2 x half> %old, i32 %src, float %scale, i32 4, i1 false)
76+
ret <2 x half> %result
77+
}
78+
79+
; CHECK: immarg value 15 out of range [0, 4)
80+
; CHECK-NEXT: %result = call <2 x half> @llvm.amdgcn.cvt.scalef32.f16.fp8(<2 x half> %old, i32 %src, float %scale, i32 15, i1 true)
81+
define <2 x half> @test_cvt_scalef32_f16_fp8_src_sel_index_way_out_of_range(<2 x half> %old, i32 %src, float %scale) {
82+
%result = call <2 x half> @llvm.amdgcn.cvt.scalef32.f16.fp8(<2 x half> %old, i32 %src, float %scale, i32 15, i1 true)
83+
ret <2 x half> %result
84+
}
85+
86+
; --------------------------------------------------------------------
87+
; llvm.amdgcn.cvt.scalef32.pk.fp4.f32 - dst_sel_index out of range
88+
; --------------------------------------------------------------------
89+
90+
; CHECK: immarg value 4 out of range [0, 4)
91+
; CHECK-NEXT: %result = call i32 @llvm.amdgcn.cvt.scalef32.pk.fp4.f32(i32 %old, float %src0, float %src1, float %scale, i32 4)
92+
define i32 @test_cvt_scalef32_pk_fp4_f32_dst_sel_index_out_of_range(i32 %old, float %src0, float %src1, float %scale) {
93+
%result = call i32 @llvm.amdgcn.cvt.scalef32.pk.fp4.f32(i32 %old, float %src0, float %src1, float %scale, i32 4)
94+
ret i32 %result
95+
}
96+
97+
; CHECK: immarg value 8 out of range [0, 4)
98+
; CHECK-NEXT: %result = call i32 @llvm.amdgcn.cvt.scalef32.pk.fp4.f32(i32 %old, float %src0, float %src1, float %scale, i32 8)
99+
define i32 @test_cvt_scalef32_pk_fp4_f32_dst_sel_index_way_out_of_range(i32 %old, float %src0, float %src1, float %scale) {
100+
%result = call i32 @llvm.amdgcn.cvt.scalef32.pk.fp4.f32(i32 %old, float %src0, float %src1, float %scale, i32 8)
101+
ret i32 %result
102+
}
103+
104+
; --------------------------------------------------------------------
105+
; llvm.amdgcn.cvt.scalef32.pk.fp4.f16 - dest_sel_index out of range
106+
; --------------------------------------------------------------------
107+
108+
; CHECK: immarg value 4 out of range [0, 4)
109+
; CHECK-NEXT: %result = call i32 @llvm.amdgcn.cvt.scalef32.pk.fp4.f16(i32 %old, <2 x half> %src, float %scale, i32 4)
110+
define i32 @test_cvt_scalef32_pk_fp4_f16_dest_sel_index_out_of_range(i32 %old, <2 x half> %src, float %scale) {
111+
%result = call i32 @llvm.amdgcn.cvt.scalef32.pk.fp4.f16(i32 %old, <2 x half> %src, float %scale, i32 4)
112+
ret i32 %result
113+
}
114+
115+
; CHECK: immarg value 12 out of range [0, 4)
116+
; CHECK-NEXT: %result = call i32 @llvm.amdgcn.cvt.scalef32.pk.fp4.f16(i32 %old, <2 x half> %src, float %scale, i32 12)
117+
define i32 @test_cvt_scalef32_pk_fp4_f16_dest_sel_index_way_out_of_range(i32 %old, <2 x half> %src, float %scale) {
118+
%result = call i32 @llvm.amdgcn.cvt.scalef32.pk.fp4.f16(i32 %old, <2 x half> %src, float %scale, i32 12)
119+
ret i32 %result
120+
}
121+
122+
; --------------------------------------------------------------------
123+
; llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f16 - dst_sel_index out of range
124+
; --------------------------------------------------------------------
125+
126+
; CHECK: immarg value 4 out of range [0, 4)
127+
; CHECK-NEXT: %result = call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f16(i32 %old, <2 x half> %src, i32 %seed, float %scale, i32 4)
128+
define i32 @test_cvt_scalef32_sr_pk_fp4_f16_dst_sel_index_out_of_range(i32 %old, <2 x half> %src, i32 %seed, float %scale) {
129+
%result = call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f16(i32 %old, <2 x half> %src, i32 %seed, float %scale, i32 4)
130+
ret i32 %result
131+
}
132+
133+
; CHECK: immarg value 9 out of range [0, 4)
134+
; CHECK-NEXT: %result = call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f16(i32 %old, <2 x half> %src, i32 %seed, float %scale, i32 9)
135+
define i32 @test_cvt_scalef32_sr_pk_fp4_f16_dst_sel_index_way_out_of_range(i32 %old, <2 x half> %src, i32 %seed, float %scale) {
136+
%result = call i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f16(i32 %old, <2 x half> %src, i32 %seed, float %scale, i32 9)
137+
ret i32 %result
138+
}
139+
140+
declare i32 @llvm.amdgcn.cvt.sr.fp8.f16(half, i32, i32, i32)
141+
declare i32 @llvm.amdgcn.cvt.sr.bf8.f16(half, i32, i32, i32)
142+
declare <8 x half> @llvm.amdgcn.cvt.scale.pk8.f16.fp8(<2 x i32>, i32, i32)
143+
declare float @llvm.amdgcn.cvt.scalef32.f32.fp8(i32, float, i32)
144+
declare <2 x half> @llvm.amdgcn.cvt.scalef32.f16.fp8(<2 x half>, i32, float, i32, i1)
145+
declare i32 @llvm.amdgcn.cvt.scalef32.pk.fp4.f32(i32, float, float, float, i32)
146+
declare i32 @llvm.amdgcn.cvt.scalef32.pk.fp4.f16(i32, <2 x half>, float, i32)
147+
declare i32 @llvm.amdgcn.cvt.scalef32.sr.pk.fp4.f16(i32, <2 x half>, i32, float, i32)

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