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[X86] SimplifyDemandedBitsForTargetNode - add handling for VPMADD52L/VPMADD52H (#155494)
Resolves #155387. The X86ISD::VPMADD52L/VPMADD52H nodes only demand the lower 52 bits of operands 0 / 1.
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‎llvm/lib/Target/X86/X86ISelLowering.cpp

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@@ -44957,6 +44957,24 @@ bool X86TargetLowering::SimplifyDemandedBitsForTargetNode(
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Known.Zero.setLowBits(Known2.countMinTrailingZeros());
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return false;
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}
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case X86ISD::VPMADD52L:
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case X86ISD::VPMADD52H: {
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KnownBits KnownOp0, KnownOp1;
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SDValue Op0 = Op.getOperand(0);
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SDValue Op1 = Op.getOperand(1);
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// Only demand the lower 52-bits of operands 0 / 1 (and all 64-bits of
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// operand 2).
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APInt Low52Bits = APInt::getLowBitsSet(BitWidth, 52);
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if (SimplifyDemandedBits(Op0, Low52Bits, OriginalDemandedElts, KnownOp0,
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TLO, Depth + 1))
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return true;
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if (SimplifyDemandedBits(Op1, Low52Bits, OriginalDemandedElts, KnownOp1,
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TLO, Depth + 1))
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return true;
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// TODO: Compute the known bits for VPMADD52L/VPMADD52H.
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break;
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}
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}
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return TargetLowering::SimplifyDemandedBitsForTargetNode(
@@ -60073,6 +60091,19 @@ static SDValue combineVPMADD(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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// Simplify VPMADD52L/VPMADD52H operations.
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static SDValue combineVPMADD52LH(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI) {
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MVT VT = N->getSimpleValueType(0);
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unsigned NumEltBits = VT.getScalarSizeInBits();
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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if (TLI.SimplifyDemandedBits(SDValue(N, 0), APInt::getAllOnes(NumEltBits),
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DCI))
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return SDValue(N, 0);
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return SDValue();
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}
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static SDValue combineEXTEND_VECTOR_INREG(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
@@ -60710,6 +60741,8 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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case X86ISD::PMULUDQ: return combinePMULDQ(N, DAG, DCI, Subtarget);
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case X86ISD::VPMADDUBSW:
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case X86ISD::VPMADDWD: return combineVPMADD(N, DAG, DCI);
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case X86ISD::VPMADD52L:
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case X86ISD::VPMADD52H: return combineVPMADD52LH(N, DAG, DCI);
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case X86ISD::KSHIFTL:
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case X86ISD::KSHIFTR: return combineKSHIFT(N, DAG, DCI);
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case ISD::FP16_TO_FP: return combineFP16_TO_FP(N, DAG, Subtarget);

‎llvm/test/CodeGen/X86/combine-vpmadd52.ll

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@@ -0,0 +1,106 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512ifma,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX512
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avxifma | FileCheck %s --check-prefixes=CHECK,AVX
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define <2 x i64> @test1_vpmadd52l(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2) {
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; AVX512-LABEL: test1_vpmadd52l:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpmadd52luq %xmm2, %xmm1, %xmm0
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; AVX512-NEXT: retq
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;
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; AVX-LABEL: test1_vpmadd52l:
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; AVX: # %bb.0:
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; AVX-NEXT: {vex} vpmadd52luq %xmm2, %xmm1, %xmm0
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; AVX-NEXT: retq
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%and = and <2 x i64> %x1, splat (i64 4503599627370495) ; (1LL << 52) - 1
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%1 = call <2 x i64> @llvm.x86.avx512.vpmadd52l.uq.128(<2 x i64> %x0, <2 x i64> %and, <2 x i64> %x2)
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ret <2 x i64> %1
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}
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define <2 x i64> @test2_vpmadd52l(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2) {
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; AVX512-LABEL: test2_vpmadd52l:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpmadd52luq %xmm2, %xmm1, %xmm0
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; AVX512-NEXT: retq
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;
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; AVX-LABEL: test2_vpmadd52l:
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; AVX: # %bb.0:
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; AVX-NEXT: {vex} vpmadd52luq %xmm2, %xmm1, %xmm0
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; AVX-NEXT: retq
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%and = and <2 x i64> %x2, splat (i64 4503599627370495) ; (1LL << 52) - 1
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%1 = call <2 x i64> @llvm.x86.avx512.vpmadd52l.uq.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %and)
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ret <2 x i64> %1
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}
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define <2 x i64> @test3_vpmadd52l(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2) {
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; AVX512-LABEL: test3_vpmadd52l:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpmadd52luq %xmm2, %xmm1, %xmm0
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; AVX512-NEXT: retq
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;
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; AVX-LABEL: test3_vpmadd52l:
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; AVX: # %bb.0:
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; AVX-NEXT: {vex} vpmadd52luq %xmm2, %xmm1, %xmm0
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; AVX-NEXT: retq
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%and = and <2 x i64> %x1, splat (i64 4503599627370495) ; (1LL << 52) - 1
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%or = or <2 x i64> %x2, splat (i64 4503599627370496) ; 1LL << 52
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%1 = call <2 x i64> @llvm.x86.avx512.vpmadd52l.uq.128(<2 x i64> %x0, <2 x i64> %and, <2 x i64> %or)
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ret <2 x i64> %1
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}
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define <2 x i64> @test_vpmadd52l_wrong_bits(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2) {
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; AVX512-LABEL: test_vpmadd52l_wrong_bits:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm1
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; AVX512-NEXT: vporq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm2, %xmm2
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; AVX512-NEXT: vpmadd52luq %xmm2, %xmm1, %xmm0
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; AVX512-NEXT: retq
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;
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; AVX-LABEL: test_vpmadd52l_wrong_bits:
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; AVX: # %bb.0:
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; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
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; AVX-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
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; AVX-NEXT: {vex} vpmadd52luq %xmm2, %xmm1, %xmm0
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; AVX-NEXT: retq
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%and = and <2 x i64> %x1, splat (i64 2251799813685247) ; (1LL << 51) - 1
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%or = or <2 x i64> %x2, splat (i64 2251799813685248) ; 1LL << 51
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%1 = call <2 x i64> @llvm.x86.avx512.vpmadd52l.uq.128(<2 x i64> %x0, <2 x i64> %and, <2 x i64> %or)
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ret <2 x i64> %1
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}
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define <2 x i64> @test_vpmadd52l_wrong_op(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2) {
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; AVX512-LABEL: test_vpmadd52l_wrong_op:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
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; AVX512-NEXT: vpmadd52luq %xmm2, %xmm1, %xmm0
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; AVX512-NEXT: retq
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;
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; AVX-LABEL: test_vpmadd52l_wrong_op:
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; AVX: # %bb.0:
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; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
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; AVX-NEXT: {vex} vpmadd52luq %xmm2, %xmm1, %xmm0
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; AVX-NEXT: retq
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%and = and <2 x i64> %x1, splat (i64 4503599627370495) ; (1LL << 52) - 1
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%1 = call <2 x i64> @llvm.x86.avx512.vpmadd52l.uq.128(<2 x i64> %and, <2 x i64> %x1, <2 x i64> %x2)
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ret <2 x i64> %1
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}
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define <2 x i64> @test_vpmadd52h(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2) {
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; AVX512-LABEL: test_vpmadd52h:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpmadd52huq %xmm2, %xmm1, %xmm0
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; AVX512-NEXT: retq
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;
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; AVX-LABEL: test_vpmadd52h:
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; AVX: # %bb.0:
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; AVX-NEXT: {vex} vpmadd52huq %xmm2, %xmm1, %xmm0
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; AVX-NEXT: retq
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%and = and <2 x i64> %x1, splat (i64 4503599627370495) ; (1LL << 52) - 1
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%or = or <2 x i64> %x2, splat (i64 4503599627370496) ; 1LL << 52
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%1 = call <2 x i64> @llvm.x86.avx512.vpmadd52h.uq.128(<2 x i64> %x0, <2 x i64> %and, <2 x i64> %or)
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ret <2 x i64> %1
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}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; CHECK: {{.*}}

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