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Address review comment
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4 files changed

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‎llvm/lib/Target/X86/X86InstrAMX.td‎

Lines changed: 34 additions & 81 deletions
Original file line numberDiff line numberDiff line change
@@ -345,24 +345,31 @@ let Predicates = [HasAMXTILE, In64BitMode], isPseudo = true, SchedRW = [WriteSys
345345
def PTILEPAIRLOAD : PseudoI<(outs TILEPair:$dst), (ins opaquemem:$src), []>;
346346
}
347347

348-
let Predicates = [HasAMXTRANSPOSE, In64BitMode] in {
349-
let SchedRW = [WriteSystem] in {
350-
def T2RPNTLVWZ0 : I<0x6e, MRMSrcMemFSIB, (outs TILEPair:$dst),
351-
(ins sibmem:$src), "t2rpntlvwz0\t{$src, $dst|$dst, $src}",
352-
[]>, VEX, T8, PS;
348+
multiclass T2RPNTLVW_Base<bits<8> op1, bits<8> op2, string rs, string suffix> {
349+
def Z0#rs#suffix : I<op1, MRMSrcMemFSIB, (outs TILEPair:$dst), (ins sibmem:$src),
350+
"t2rpntlvwz0" #!tolower(rs)# "\t{$src, $dst|$dst, $src}", []>, PS;
351+
def Z0#rs#T1#suffix : I<op2, MRMSrcMemFSIB, (outs TILEPair:$dst), (ins sibmem:$src),
352+
"t2rpntlvwz0" #!tolower(rs)# "t1\t{$src, $dst|$dst, $src}", []>, PS;
353+
def Z1#rs#suffix : I<op1, MRMSrcMemFSIB, (outs TILEPair:$dst), (ins sibmem:$src),
354+
"t2rpntlvwz1" #!tolower(rs)# "\t{$src, $dst|$dst, $src}", []>, PD;
355+
def Z1#rs#T1#suffix : I<op2, MRMSrcMemFSIB, (outs TILEPair:$dst), (ins sibmem:$src),
356+
"t2rpntlvwz1" #!tolower(rs)# "t1\t{$src, $dst|$dst, $src}", []>, PD;
357+
}
353358

354-
def T2RPNTLVWZ0T1 : I<0x6f, MRMSrcMemFSIB, (outs TILEPair:$dst),
355-
(ins sibmem:$src), "t2rpntlvwz0t1\t{$src, $dst|$dst, $src}",
356-
[]>, VEX, T8, PS;
359+
let Predicates = [HasAMXTRANSPOSE, In64BitMode], SchedRW = [WriteSystem] in
360+
defm T2RPNTLVW : T2RPNTLVW_Base<0x6e, 0x6f, "", "">, T8, VEX;
357361

358-
def T2RPNTLVWZ1 : I<0x6e, MRMSrcMemFSIB, (outs TILEPair:$dst),
359-
(ins sibmem:$src), "t2rpntlvwz1\t{$src, $dst|$dst, $src}",
360-
[]>, VEX, T8, PD;
362+
let Predicates = [HasAMXTRANSPOSE, HasEGPR, In64BitMode], SchedRW = [WriteSystem] in
363+
defm T2RPNTLVW : T2RPNTLVW_Base<0x6e, 0x6f, "", "_EVEX">, T8, EVEX, NoCD8;
361364

362-
def T2RPNTLVWZ1T1 : I<0x6f, MRMSrcMemFSIB, (outs TILEPair:$dst),
363-
(ins sibmem:$src), "t2rpntlvwz1t1\t{$src, $dst|$dst, $src}",
364-
[]>, VEX, T8, PD;
365+
let Predicates = [HasAMXMOVRS, HasAMXTRANSPOSE, In64BitMode], SchedRW = [WriteSystem] in
366+
defm T2RPNTLVW : T2RPNTLVW_Base<0xf8, 0xf9, "RS", "">, T_MAP5, VEX;
365367

368+
let Predicates = [HasAMXMOVRS, HasAMXTRANSPOSE, HasEGPR, In64BitMode], SchedRW = [WriteSystem] in
369+
defm T2RPNTLVW : T2RPNTLVW_Base<0xf8, 0xf9, "RS", "_EVEX">, T_MAP5, EVEX, NoCD8;
370+
371+
let Predicates = [HasAMXTRANSPOSE, In64BitMode] in {
372+
let SchedRW = [WriteSystem] in {
366373
def TTRANSPOSED : I<0x5f, MRMSrcReg, (outs TILE:$dst), (ins TILE:$src),
367374
"ttransposed\t{$src, $dst|$dst, $src}", []>, VEX, T8, XS;
368375
let isPseudo = true in {
@@ -491,22 +498,6 @@ let Predicates = [HasAMXCOMPLEX, HasAMXTRANSPOSE, In64BitMode], SchedRW = [Write
491498
}
492499

493500
let Predicates = [HasAMXMOVRS, HasAMXTRANSPOSE, In64BitMode], SchedRW = [WriteSystem] in {
494-
def T2RPNTLVWZ0RS : I<0xf8, MRMSrcMemFSIB, (outs TILEPair:$dst),
495-
(ins sibmem:$src1),
496-
"t2rpntlvwz0rs\t{$src1, $dst|$dst, $src1}",
497-
[]>, VEX, T_MAP5;
498-
def T2RPNTLVWZ0RST1 : I<0xf9, MRMSrcMemFSIB, (outs TILEPair:$dst),
499-
(ins sibmem:$src1),
500-
"t2rpntlvwz0rst1\t{$src1, $dst|$dst, $src1}",
501-
[]>, VEX, T_MAP5;
502-
def T2RPNTLVWZ1RS : I<0xf8, MRMSrcMemFSIB, (outs TILEPair:$dst),
503-
(ins sibmem:$src1),
504-
"t2rpntlvwz1rs\t{$src1, $dst|$dst, $src1}",
505-
[]>, VEX, T_MAP5, PD;
506-
def T2RPNTLVWZ1RST1 : I<0xf9, MRMSrcMemFSIB, (outs TILEPair:$dst),
507-
(ins sibmem:$src1),
508-
"t2rpntlvwz1rst1\t{$src1, $dst|$dst, $src1}",
509-
[]>, VEX, T_MAP5, PD;
510501
let isPseudo = true in {
511502
def PT2RPNTLVWZ0RSV : PseudoI<(outs TILEPair:$dst),
512503
(ins GR16:$src1, GR16:$src2, GR16:$src3, opaquemem:$src4),
@@ -529,16 +520,20 @@ let Predicates = [HasAMXMOVRS, HasAMXTRANSPOSE, In64BitMode], SchedRW = [WriteSy
529520
}
530521
} // HasAMXMOVRS, HasAMXTRANSPOSE
531522

532-
let Predicates = [HasAMXMOVRS, In64BitMode], SchedRW = [WriteSystem] in {
533-
def TILELOADDRS : I<0x4a, MRMSrcMemFSIB, (outs TILE:$dst),
534-
(ins sibmem:$src1),
535-
"tileloaddrs\t{$src1, $dst|$dst, $src1}",
536-
[]>, VEX, T8, XD;
537-
def TILELOADDRST1 : I<0x4a, MRMSrcMemFSIB, (outs TILE:$dst),
538-
(ins sibmem:$src1),
539-
"tileloaddrst1\t{$src1, $dst|$dst, $src1}",
540-
[]>, VEX, T8, PD;
523+
multiclass TILELOADDRS_Base<string suffix> {
524+
def suffix : I<0x4a, MRMSrcMemFSIB, (outs TILE:$dst), (ins sibmem:$src1),
525+
"tileloaddrs\t{$src1, $dst|$dst, $src1}", []>, T8, XD;
526+
def T1#suffix : I<0x4a, MRMSrcMemFSIB, (outs TILE:$dst), (ins sibmem:$src1),
527+
"tileloaddrst1\t{$src1, $dst|$dst, $src1}", []>, T8, PD;
528+
}
529+
530+
let Predicates = [HasAMXMOVRS, In64BitMode], SchedRW = [WriteSystem] in
531+
defm TILELOADDRS : TILELOADDRS_Base<"">, VEX;
541532

533+
let Predicates = [HasAMXMOVRS, HasEGPR, In64BitMode], SchedRW = [WriteSystem] in
534+
defm TILELOADDRS : TILELOADDRS_Base<"_EVEX">, EVEX, NoCD8;
535+
536+
let Predicates = [HasAMXMOVRS, In64BitMode], SchedRW = [WriteSystem] in {
542537
let isPseudo = true, mayLoad = 1 in {
543538
def PTILELOADDRSV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
544539
GR16:$src2,
@@ -554,48 +549,6 @@ let Predicates = [HasAMXMOVRS, In64BitMode], SchedRW = [WriteSystem] in {
554549
}
555550
} // HasAMXMOVRS, In64BitMode
556551

557-
let Predicates = [HasAMXTRANSPOSE, HasEGPR, In64BitMode], SchedRW = [WriteSystem] in {
558-
def T2RPNTLVWZ0_EVEX : I<0x6e, MRMSrcMemFSIB, (outs TILEPair:$dst),
559-
(ins sibmem:$src), "t2rpntlvwz0\t{$src, $dst|$dst, $src}",
560-
[]>, EVEX, NoCD8, T8, PS;
561-
562-
def T2RPNTLVWZ0T1_EVEX : I<0x6f, MRMSrcMemFSIB, (outs TILEPair:$dst),
563-
(ins sibmem:$src), "t2rpntlvwz0t1\t{$src, $dst|$dst, $src}",
564-
[]>, EVEX, NoCD8, T8, PS;
565-
566-
def T2RPNTLVWZ1_EVEX : I<0x6e, MRMSrcMemFSIB, (outs TILEPair:$dst),
567-
(ins sibmem:$src), "t2rpntlvwz1\t{$src, $dst|$dst, $src}",
568-
[]>, EVEX, NoCD8, T8, PD;
569-
570-
def T2RPNTLVWZ1T1_EVEX : I<0x6f, MRMSrcMemFSIB, (outs TILEPair:$dst),
571-
(ins sibmem:$src), "t2rpntlvwz1t1\t{$src, $dst|$dst, $src}",
572-
[]>, EVEX, NoCD8, T8, PD;
573-
} // HasAMXTRANSPOSE, HasEGPR, In64BitMode
574-
575-
let Predicates = [HasAMXMOVRS, HasAMXTRANSPOSE, HasEGPR, In64BitMode], SchedRW = [WriteSystem] in {
576-
def T2RPNTLVWZ0RS_EVEX : I<0xf8, MRMSrcMemFSIB, (outs TILEPair:$dst),
577-
(ins sibmem:$src1), "t2rpntlvwz0rs\t{$src1, $dst|$dst, $src1}",
578-
[]>, EVEX, NoCD8, T_MAP5;
579-
def T2RPNTLVWZ0RST1_EVEX : I<0xf9, MRMSrcMemFSIB, (outs TILEPair:$dst),
580-
(ins sibmem:$src1), "t2rpntlvwz0rst1\t{$src1, $dst|$dst, $src1}",
581-
[]>, EVEX, NoCD8, T_MAP5;
582-
def T2RPNTLVWZ1RS_EVEX : I<0xf8, MRMSrcMemFSIB, (outs TILEPair:$dst),
583-
(ins sibmem:$src1), "t2rpntlvwz1rs\t{$src1, $dst|$dst, $src1}",
584-
[]>, EVEX, NoCD8, T_MAP5, PD;
585-
def T2RPNTLVWZ1RST1_EVEX : I<0xf9, MRMSrcMemFSIB, (outs TILEPair:$dst),
586-
(ins sibmem:$src1), "t2rpntlvwz1rst1\t{$src1, $dst|$dst, $src1}",
587-
[]>, EVEX, NoCD8, T_MAP5, PD;
588-
} // HasAMXMOVRS, HasAMXTRANSPOSE, HasEGPR, In64BitMode
589-
590-
let Predicates = [HasAMXMOVRS, HasEGPR, In64BitMode], SchedRW = [WriteSystem] in {
591-
def TILELOADDRS_EVEX : I<0x4a, MRMSrcMemFSIB, (outs TILE:$dst),
592-
(ins sibmem:$src1), "tileloaddrs\t{$src1, $dst|$dst, $src1}",
593-
[]>, EVEX, NoCD8, T8, XD;
594-
def TILELOADDRST1_EVEX : I<0x4a, MRMSrcMemFSIB, (outs TILE:$dst),
595-
(ins sibmem:$src1), "tileloaddrst1\t{$src1, $dst|$dst, $src1}",
596-
[]>, EVEX, NoCD8, T8, PD;
597-
} // HasAMXMOVRS, HasEGPR, In64BitMode
598-
599552
multiclass m_tcvtrowd2ps {
600553
let Predicates = [HasAMXAVX512, HasAVX10_2_512, In64BitMode] in {
601554
let SchedRW = [WriteSystem] in {

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