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vishruth-thimmaiahvishruth-thimmaiah
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add extra tests
Signed-off-by: vishruth-thimmaiah <[email protected]>
1 parent a65aab4 commit 8692dc8

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2 files changed

+110
-13
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2 files changed

+110
-13
lines changed

‎clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp‎

Lines changed: 7 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -310,11 +310,9 @@ static mlir::Value emitX86vpcom(CIRGenBuilderTy &builder, mlir::Location loc,
310310
mlir::Value op1 = ops[1];
311311

312312
cir::VectorType ty = cast<cir::VectorType>(op0.getType());
313-
mlir::Type elementTy = ty.getElementType();
313+
cir::IntType elementTy = cast<cir::IntType>(ty.getElementType());
314314

315-
uint64_t imm =
316-
ops[2].getDefiningOp<cir::ConstantOp>().getIntValue().getZExtValue() &
317-
0x7;
315+
uint64_t imm = CIRGenFunction::getZExtIntValueFromConstOp(ops[2]) & 0x7;
318316

319317
cir::CmpOpKind pred;
320318
switch (imm) {
@@ -339,8 +337,7 @@ static mlir::Value emitX86vpcom(CIRGenBuilderTy &builder, mlir::Location loc,
339337
case 0x6:
340338
return builder.getNullValue(ty, loc); // FALSE
341339
case 0x7: {
342-
llvm::APInt allOnes =
343-
llvm::APInt::getAllOnes(cast<cir::IntType>(elementTy).getWidth());
340+
llvm::APInt allOnes = llvm::APInt::getAllOnes(elementTy.getWidth());
344341
return cir::VecSplatOp::create(
345342
builder, loc, ty,
346343
builder.getConstAPInt(loc, elementTy, allOnes)); // TRUE
@@ -349,8 +346,10 @@ static mlir::Value emitX86vpcom(CIRGenBuilderTy &builder, mlir::Location loc,
349346
llvm_unreachable("Unexpected XOP vpcom/vpcomu predicate");
350347
}
351348

352-
if (!isSigned) {
353-
elementTy = builder.getUIntNTy(cast<cir::IntType>(elementTy).getWidth());
349+
if ((!isSigned && elementTy.isSigned()) ||
350+
(isSigned && elementTy.isUnsigned())) {
351+
elementTy = elementTy.isSigned() ? builder.getUIntNTy(elementTy.getWidth())
352+
: builder.getSIntNTy(elementTy.getWidth());
354353
ty = cir::VectorType::get(elementTy, ty.getSize());
355354
op0 = builder.createBitcast(op0, ty);
356355
op1 = builder.createBitcast(op1, ty);

‎clang/test/CIR/CodeGenBuiltins/X86/xop-builtins.c‎

Lines changed: 103 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -93,9 +93,7 @@ __m128i test_mm_roti_epi64(__m128i a) {
9393

9494
__m128i test_mm_com_epu8(__m128i a, __m128i b) {
9595
// CIR-LABEL: test_mm_com_epu8
96-
// CIR: %[[A:.*]] = cir.cast bitcast %{{.*}} : !cir.vector<16 x !s8i> -> !cir.vector<16 x !u8i>
97-
// CIR: %[[B:.*]] = cir.cast bitcast %{{.*}} : !cir.vector<16 x !s8i> -> !cir.vector<16 x !u8i>
98-
// CIR: %[[CMP:.*]] = cir.vec.cmp(lt, %[[A]], %[[B]]) : !cir.vector<16 x !u8i>, !cir.vector<16 x !s8i>
96+
// CIR: %[[CMP:.*]] = cir.vec.cmp(lt, %{{.*}}, %{{.*}}) : !cir.vector<16 x !u8i>, !cir.vector<16 x !s8i>
9997
// CIR: %[[RES:.*]] = cir.cast bitcast %[[CMP]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !s64i>
10098

10199
// LLVM-LABEL: test_mm_com_epu8
@@ -161,7 +159,62 @@ __m128i test_mm_com_epu64(__m128i a, __m128i b) {
161159
// OGCG-LABEL: test_mm_com_epu64
162160
// OGCG: %[[CMP:.*]] = icmp ult <2 x i64> %{{.*}}, %{{.*}}
163161
// OGCG: %[[RES:.*]] = sext <2 x i1> %[[CMP]] to <2 x i64>
164-
return _mm_com_epu64(a, b, 0);
162+
a = _mm_com_epu64(a, b, 0);
163+
164+
// CIR: %[[VAL1:.*]] = cir.cast bitcast %{{.*}} : !cir.vector<2 x !s64i> -> !cir.vector<2 x !u64i>
165+
// CIR: %[[VAL2:.*]] = cir.cast bitcast %{{.*}} : !cir.vector<2 x !s64i> -> !cir.vector<2 x !u64i>
166+
// CIR: %[[CMP:.*]] = cir.vec.cmp(le, %[[VAL1]], %[[VAL2]]) : !cir.vector<2 x !u64i>, !cir.vector<2 x !s64i>
167+
168+
// LLVM: %[[CMP:.*]] = icmp ule <2 x i64> %{{.*}}, %{{.*}}
169+
// LLVM: %[[RES:.*]] = sext <2 x i1> %[[CMP]] to <2 x i64>
170+
171+
// OGCG: %[[CMP:.*]] = icmp ule <2 x i64> %{{.*}}, %{{.*}}
172+
// OGCG: %[[RES:.*]] = sext <2 x i1> %[[CMP]] to <2 x i64>
173+
a = _mm_com_epu64(a, b, 1);
174+
175+
// CIR: %[[VAL1:.*]] = cir.cast bitcast %{{.*}} : !cir.vector<2 x !s64i> -> !cir.vector<2 x !u64i>
176+
// CIR: %[[VAL2:.*]] = cir.cast bitcast %{{.*}} : !cir.vector<2 x !s64i> -> !cir.vector<2 x !u64i>
177+
// CIR: %[[CMP:.*]] = cir.vec.cmp(gt, %[[VAL1]], %[[VAL2]]) : !cir.vector<2 x !u64i>, !cir.vector<2 x !s64i>
178+
179+
// LLVM: %[[CMP:.*]] = icmp ugt <2 x i64> %{{.*}}, %{{.*}}
180+
// LLVM: %[[RES:.*]] = sext <2 x i1> %[[CMP]] to <2 x i64>
181+
182+
// OGCG: %[[CMP:.*]] = icmp ugt <2 x i64> %{{.*}}, %{{.*}}
183+
// OGCG: %[[RES:.*]] = sext <2 x i1> %[[CMP]] to <2 x i64>
184+
a = _mm_com_epu64(a, b, 2);
185+
186+
// CIR: %[[VAL1:.*]] = cir.cast bitcast %{{.*}} : !cir.vector<2 x !s64i> -> !cir.vector<2 x !u64i>
187+
// CIR: %[[VAL2:.*]] = cir.cast bitcast %{{.*}} : !cir.vector<2 x !s64i> -> !cir.vector<2 x !u64i>
188+
// CIR: %[[CMP:.*]] = cir.vec.cmp(ge, %[[VAL1]], %[[VAL2]]) : !cir.vector<2 x !u64i>, !cir.vector<2 x !s64i>
189+
190+
// LLVM: %[[CMP:.*]] = icmp uge <2 x i64> %{{.*}}, %{{.*}}
191+
// LLVM: %[[RES:.*]] = sext <2 x i1> %[[CMP]] to <2 x i64>
192+
193+
// OGCG: %[[CMP:.*]] = icmp uge <2 x i64> %{{.*}}, %{{.*}}
194+
// OGCG: %[[RES:.*]] = sext <2 x i1> %[[CMP]] to <2 x i64>
195+
a = _mm_com_epu64(a, b, 3);
196+
197+
// CIR: %[[VAL1:.*]] = cir.cast bitcast %{{.*}} : !cir.vector<2 x !s64i> -> !cir.vector<2 x !u64i>
198+
// CIR: %[[VAL2:.*]] = cir.cast bitcast %{{.*}} : !cir.vector<2 x !s64i> -> !cir.vector<2 x !u64i>
199+
// CIR: %[[CMP:.*]] = cir.vec.cmp(eq, %[[VAL1]], %[[VAL2]]) : !cir.vector<2 x !u64i>, !cir.vector<2 x !s64i>
200+
201+
// LLVM: %[[CMP:.*]] = icmp eq <2 x i64> %{{.*}}, %{{.*}}
202+
// LLVM: %[[RES:.*]] = sext <2 x i1> %[[CMP]] to <2 x i64>
203+
204+
// OGCG: %[[CMP:.*]] = icmp eq <2 x i64> %{{.*}}, %{{.*}}
205+
// OGCG: %[[RES:.*]] = sext <2 x i1> %[[CMP]] to <2 x i64>
206+
a = _mm_com_epu64(a, b, 4);
207+
208+
// CIR: %[[VAL1:.*]] = cir.cast bitcast %{{.*}} : !cir.vector<2 x !s64i> -> !cir.vector<2 x !u64i>
209+
// CIR: %[[VAL2:.*]] = cir.cast bitcast %{{.*}} : !cir.vector<2 x !s64i> -> !cir.vector<2 x !u64i>
210+
// CIR: %[[CMP:.*]] = cir.vec.cmp(ne, %[[VAL1]], %[[VAL2]]) : !cir.vector<2 x !u64i>, !cir.vector<2 x !s64i>
211+
212+
// LLVM: %[[CMP:.*]] = icmp ne <2 x i64> %{{.*}}, %{{.*}}
213+
// LLVM: %[[RES:.*]] = sext <2 x i1> %[[CMP]] to <2 x i64>
214+
215+
// OGCG: %[[CMP:.*]] = icmp ne <2 x i64> %{{.*}}, %{{.*}}
216+
// OGCG: %[[RES:.*]] = sext <2 x i1> %[[CMP]] to <2 x i64>
217+
return _mm_com_epu64(a, b, 5);
165218
}
166219

167220
__m128i test_mm_com_epi8(__m128i a, __m128i b) {
@@ -226,7 +279,52 @@ __m128i test_mm_com_epi64(__m128i a, __m128i b) {
226279
// OGCG-LABEL: test_mm_com_epi64
227280
// OGCG: %[[CMP:.*]] = icmp slt <2 x i64> %{{.*}}, %{{.*}}
228281
// OGCG: %[[RES:.*]] = sext <2 x i1> %[[CMP]] to <2 x i64>
229-
return _mm_com_epi64(a, b, 0);
282+
a = _mm_com_epi64(a, b, 0);
283+
284+
// CIR: %[[CMP1:.*]] = cir.vec.cmp(le, %{{.*}}, %{{.*}}) : !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>
285+
286+
// LLVM: %[[CMP1:.*]] = icmp sle <2 x i64> %{{.*}}, %{{.*}}
287+
// LLVM: %[[RES1:.*]] = sext <2 x i1> %[[CMP1]] to <2 x i64>
288+
289+
// OGCG: %[[CMP1:.*]] = icmp sle <2 x i64> %{{.*}}, %{{.*}}
290+
// OGCG: %[[RES1:.*]] = sext <2 x i1> %[[CMP1]] to <2 x i64>
291+
a = _mm_com_epi64(a, b, 1);
292+
293+
// CIR: %[[CMP1:.*]] = cir.vec.cmp(gt, %{{.*}}, %{{.*}}) : !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>
294+
295+
// LLVM: %[[CMP1:.*]] = icmp sgt <2 x i64> %{{.*}}, %{{.*}}
296+
// LLVM: %[[RES1:.*]] = sext <2 x i1> %[[CMP1]] to <2 x i64>
297+
298+
// OGCG: %[[CMP1:.*]] = icmp sgt <2 x i64> %{{.*}}, %{{.*}}
299+
// OGCG: %[[RES1:.*]] = sext <2 x i1> %[[CMP1]] to <2 x i64>
300+
a = _mm_com_epi64(a, b, 2);
301+
302+
// CIR: %[[CMP1:.*]] = cir.vec.cmp(ge, %{{.*}}, %{{.*}}) : !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>
303+
304+
// LLVM: %[[CMP1:.*]] = icmp sge <2 x i64> %{{.*}}, %{{.*}}
305+
// LLVM: %[[RES1:.*]] = sext <2 x i1> %[[CMP1]] to <2 x i64>
306+
307+
// OGCG: %[[CMP1:.*]] = icmp sge <2 x i64> %{{.*}}, %{{.*}}
308+
// OGCG: %[[RES1:.*]] = sext <2 x i1> %[[CMP1]] to <2 x i64>
309+
a = _mm_com_epi64(a, b, 3);
310+
311+
// CIR: %[[CMP1:.*]] = cir.vec.cmp(eq, %{{.*}}, %{{.*}}) : !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>
312+
313+
// LLVM: %[[CMP1:.*]] = icmp eq <2 x i64> %{{.*}}, %{{.*}}
314+
// LLVM: %[[RES1:.*]] = sext <2 x i1> %[[CMP1]] to <2 x i64>
315+
316+
// OGCG: %[[CMP1:.*]] = icmp eq <2 x i64> %{{.*}}, %{{.*}}
317+
// OGCG: %[[RES1:.*]] = sext <2 x i1> %[[CMP1]] to <2 x i64>
318+
a = _mm_com_epi64(a, b, 4);
319+
320+
// CIR: %[[CMP1:.*]] = cir.vec.cmp(ne, %{{.*}}, %{{.*}}) : !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>
321+
322+
// LLVM: %[[CMP1:.*]] = icmp ne <2 x i64> %{{.*}}, %{{.*}}
323+
// LLVM: %[[RES1:.*]] = sext <2 x i1> %[[CMP1]] to <2 x i64>
324+
325+
// OGCG: %[[CMP1:.*]] = icmp ne <2 x i64> %{{.*}}, %{{.*}}
326+
// OGCG: %[[RES1:.*]] = sext <2 x i1> %[[CMP1]] to <2 x i64>
327+
return _mm_com_epi64(a, b, 5);
230328
}
231329

232330
__m128i test_mm_com_epi32_false(__m128i a, __m128i b) {

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