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Jianhui-LiJianhui-Li
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[MLIR][XeGPU] Clean up xegpu op tests (#144592)
Test cleanup: 1) separate layout.mlir from ops.mlir for layout related test 2) remove lane layout for ops working at work item scope. 3) remove redundant test in create_tdesc/update_tdesc/prefetch. 4) remove "test_" from all test function name.
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7 files changed

+275
-381
lines changed

7 files changed

+275
-381
lines changed

‎mlir/test/Dialect/XeGPU/invalid.mlir‎

Lines changed: 48 additions & 48 deletions
Large diffs are not rendered by default.

‎mlir/test/Dialect/XeGPU/layout.mlir‎

Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,49 @@
1+
// RUN: mlir-opt %s | FileCheck %s
2+
// Verify the printed output can be parsed.
3+
// RUN: mlir-opt %s | mlir-opt | FileCheck %s
4+
// Verify the generic form can be parsed.
5+
// RUN: mlir-opt -mlir-print-op-generic %s | mlir-opt | FileCheck %s
6+
7+
// CHECK-LABEL: gpu.module @test {
8+
gpu.module @test {
9+
// CHECK: gpu.func @create_nd_tdesc_subgroup_1(%[[arg0:.*]]: memref<128x128xf32>) {
10+
gpu.func @create_nd_tdesc_subgroup_1(%src: memref<128x128xf32>) {
11+
// CHECK: %[[REG:.*]] = xegpu.create_nd_tdesc %[[arg0]][0, 0] : memref<128x128xf32> -> !xegpu.tensor_desc<128x128xf32, #xegpu.layout<sg_layout = [4, 2], sg_data = [32, 64]>>
12+
%1 = xegpu.create_nd_tdesc %src[0, 0] : memref<128x128xf32> -> !xegpu.tensor_desc<128x128xf32, #xegpu.layout<sg_layout = [4, 2], sg_data = [32, 64]>>
13+
gpu.return
14+
}
15+
16+
// CHECK: gpu.func @create_nd_tdesc_subgroup_2(%[[arg0:.*]]: memref<128x128xf32>) {
17+
gpu.func @create_nd_tdesc_subgroup_2(%src: memref<128x128xf32>) {
18+
// CHECK: %[[REG:.*]] = xegpu.create_nd_tdesc %[[arg0]][0, 0] : memref<128x128xf32> -> !xegpu.tensor_desc<128x128xf32, #xegpu.layout<sg_layout = [4, 2], sg_data = [32, 64], inst_data = [8, 16]>>
19+
%1 = xegpu.create_nd_tdesc %src[0, 0] : memref<128x128xf32> -> !xegpu.tensor_desc<128x128xf32, #xegpu.layout<sg_layout = [4, 2], sg_data = [32, 64], inst_data = [8, 16]>>
20+
gpu.return
21+
}
22+
23+
// CHECK: gpu.func @create_nd_tdesc_subgroup_3(%[[arg0:.*]]: memref<128x128xf32>) {
24+
gpu.func @create_nd_tdesc_subgroup_3(%src: memref<128x128xf32>) {
25+
// CHECK: %[[REG:.*]] = xegpu.create_nd_tdesc %[[arg0]][0, 0] : memref<128x128xf32> -> !xegpu.tensor_desc<128x128xf32, #xegpu.layout<sg_layout = [4, 2], sg_data = [32, 64], inst_data = [8, 16], lane_layout = [1, 16], lane_data = [1, 1]>>
26+
%1 = xegpu.create_nd_tdesc %src[0, 0] : memref<128x128xf32> -> !xegpu.tensor_desc<128x128xf32, #xegpu.layout<sg_layout = [4, 2], sg_data = [32, 64], inst_data = [8, 16], lane_layout = [1, 16], lane_data = [1, 1]>>
27+
gpu.return
28+
}
29+
30+
// CHECK: gpu.func @create_nd_tdesc_wg_1(%[[arg0:.*]]: memref<24x32xf32>) {
31+
gpu.func @create_nd_tdesc_wg_1(%src: memref<24x32xf32>) {
32+
// CHECK: %[[REG:.*]] = xegpu.create_nd_tdesc %arg0[0, 0] : memref<24x32xf32> -> !xegpu.tensor_desc<24x32xf32, #xegpu.layout<sg_layout = [3, 2], sg_data = [8, 16], lane_layout = [1, 16], lane_data = [8, 1]>>
33+
%1 = xegpu.create_nd_tdesc %src[0, 0] : memref<24x32xf32> -> !xegpu.tensor_desc<24x32xf32, #xegpu.layout<sg_layout = [3, 2], sg_data = [8, 16], lane_layout = [1, 16], lane_data = [8, 1]>>
34+
gpu.return
35+
}
36+
37+
gpu.func @convert_layout(%a: vector<32x64xf16>) {
38+
%2 = xegpu.convert_layout %a {srcMap = #xegpu.layout<lane_layout = [1, 16], lane_data = [2, 1]>,
39+
resMap = #xegpu.layout<lane_layout = [1, 16], lane_data = [1, 1]>} : vector<32x64xf16>
40+
gpu.return
41+
}
42+
43+
gpu.func @convert_layout_wg(%a: vector<32x64xf16>) {
44+
%2 = xegpu.convert_layout %a {srcMap = #xegpu.layout<sg_layout = [2, 4], sg_data = [16, 16], lane_layout = [1, 16], lane_data = [1, 1]>,
45+
resMap = #xegpu.layout<sg_layout = [4, 2], sg_data = [8, 32], lane_layout = [1, 16], lane_data = [1, 1]>} : vector<32x64xf16>
46+
gpu.return
47+
}
48+
49+
}

‎mlir/test/Dialect/XeGPU/ops.mlir‎

Lines changed: 100 additions & 255 deletions
Large diffs are not rendered by default.

‎mlir/test/Dialect/XeGPU/subgroup-map-propagation.mlir‎

Lines changed: 36 additions & 36 deletions
Large diffs are not rendered by default.

‎mlir/test/Dialect/XeGPU/xegpu-blocking.mlir‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
#b = #xegpu.layout<inst_data = [16, 16], lane_layout = [1, 16], lane_data = [16, 1]>
55
#c = #xegpu.layout<inst_data = [8, 16], lane_layout = [1, 16], lane_data = [8, 1]>
66
gpu.module @test_kernel {
7-
gpu.func @test_gemm_with_one_to_n_lowering(%A: memref<1024x1024xf16>, %B: memref<1024x1024xf16>, %C: memref<1024x1024xf32>) {
7+
gpu.func @gemm_with_one_to_n_lowering(%A: memref<1024x1024xf16>, %B: memref<1024x1024xf16>, %C: memref<1024x1024xf32>) {
88
%c0 = arith.constant 0 : index
99
%c16 = arith.constant 16 : index
1010
%c32 = arith.constant 32 : index
@@ -45,7 +45,7 @@ gpu.module @test_kernel {
4545
#l1 = #xegpu.layout<inst_data = [8, 16]>
4646
#l2 = #xegpu.layout<inst_data = [16, 16]>
4747
gpu.module @test_kernel {
48-
gpu.func @test_gemm_with_inst_data_only_attribute(%A: memref<1024x1024xf16>, %B: memref<1024x1024xf16>, %C: memref<1024x1024xf32>) {
48+
gpu.func @gemm_with_inst_data_only_attribute(%A: memref<1024x1024xf16>, %B: memref<1024x1024xf16>, %C: memref<1024x1024xf32>) {
4949
%c0 = arith.constant 0 : index
5050
%c16 = arith.constant 16 : index
5151
%c32 = arith.constant 32 : index
@@ -86,7 +86,7 @@ gpu.module @test_kernel {
8686
#l1 = #xegpu.layout<inst_data = [8, 16]>
8787
#l2 = #xegpu.layout<inst_data = [16, 16]>
8888
gpu.module @test_kernel {
89-
gpu.func @test_gemm_with_one_to_one_lowering(%A: memref<1024x1024xf16>, %B: memref<1024x1024xf16>, %C: memref<1024x1024xf32>) {
89+
gpu.func @gemm_with_one_to_one_lowering(%A: memref<1024x1024xf16>, %B: memref<1024x1024xf16>, %C: memref<1024x1024xf32>) {
9090
%c0 = arith.constant 0 : index
9191
%c8 = arith.constant 8 : index
9292
%c16 = arith.constant 16 : index
@@ -130,7 +130,7 @@ gpu.module @test_kernel {
130130
#b = #xegpu.layout<inst_data = [16, 16], lane_layout = [1, 16], lane_data = [16, 1]>
131131
#c = #xegpu.layout<inst_data = [8, 16], lane_layout = [1, 16], lane_data = [8, 1]>
132132
gpu.module @test_kernel {
133-
gpu.func @test_gemm_with_elemwise_preop(%A: memref<1024x1024xf16>, %B: memref<1024x1024xf16>, %C: memref<1024x1024xf32>) {
133+
gpu.func @gemm_with_elemwise_preop(%A: memref<1024x1024xf16>, %B: memref<1024x1024xf16>, %C: memref<1024x1024xf32>) {
134134
%c0 = arith.constant 0 : index
135135
%c16 = arith.constant 16 : index
136136
%c32 = arith.constant 32 : index
@@ -172,7 +172,7 @@ gpu.module @test_kernel {
172172
// -----
173173
#l = #xegpu.layout<inst_data = [8, 16]>
174174
gpu.module @test_kernel {
175-
gpu.func @test_elementwise_with_inst_data_only(%A: memref<1024x1024xf16>, %B: memref<1024x1024xf16>, %C: memref<1024x1024xf16>) {
175+
gpu.func @elementwise_with_inst_data_only(%A: memref<1024x1024xf16>, %B: memref<1024x1024xf16>, %C: memref<1024x1024xf16>) {
176176
%c0 = arith.constant 0 : index
177177
%c32 = arith.constant 32 : index
178178
%c1024 = arith.constant 1024 : index
@@ -211,7 +211,7 @@ gpu.module @test_kernel {
211211
// -----
212212
#l = #xegpu.layout<inst_data = [8]>
213213
gpu.module @test_kernel {
214-
gpu.func @test_elementwise_1D(%A: memref<1024x1024xf16>, %B: memref<1024x1024xf16>, %C: memref<1024x1024xf16>) {
214+
gpu.func @elementwise_1D(%A: memref<1024x1024xf16>, %B: memref<1024x1024xf16>, %C: memref<1024x1024xf16>) {
215215
%c0 = arith.constant 0 : index
216216
%c32 = arith.constant 32 : index
217217
%c1024 = arith.constant 1024 : index

‎mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
// RUN: mlir-opt --xegpu-wg-to-sg-distribute -split-input-file %s | FileCheck %s
22

33
gpu.module @test_round_robin_assignment {
4-
// CHECK-LABEL: test_create_nd_tdesc
4+
// CHECK-LABEL: create_nd_tdesc
55
// CHECK-SAME: %[[ARG_0:.*]]: memref<24x32xf32>
6-
gpu.func @test_create_nd_tdesc(%src: memref<24x32xf32>) {
6+
gpu.func @create_nd_tdesc(%src: memref<24x32xf32>) {
77
// CHECK-COUNT-12: xegpu.create_nd_tdesc %[[ARG_0]][%{{.*}}, %{{.*}}] : memref<24x32xf32>
88
// CHECK-SAME: -> !xegpu.tensor_desc<2x2xf32, #xegpu.layout<lane_layout = [2, 2], lane_data = [1, 1]>>
99
// CHECK-NOT: xegpu.create_nd_tdesc
@@ -12,9 +12,9 @@ gpu.module @test_round_robin_assignment {
1212
gpu.return
1313
}
1414

15-
// CHECK-LABEL: test_load_nd_tdesc
15+
// CHECK-LABEL: load_nd_tdesc
1616
// CHECK-SAME: %[[ARG_0:.*]]: memref<24x32xf32>
17-
gpu.func @test_load_nd_tdesc(%src: memref<24x32xf32>) {
17+
gpu.func @load_nd_tdesc(%src: memref<24x32xf32>) {
1818
%tdesc = xegpu.create_nd_tdesc %src[0, 0] : memref<24x32xf32>
1919
-> !xegpu.tensor_desc<24x32xf32, #xegpu.layout<sg_layout = [4, 4], sg_data = [2, 2], lane_layout = [2, 2], lane_data = [1, 1]>>
2020
// CHECK-COUNT-12: xegpu.load_nd %{{.*}}
@@ -27,9 +27,9 @@ gpu.module @test_round_robin_assignment {
2727
gpu.return
2828
}
2929

30-
// CHECK-LABEL: test_store_nd
30+
// CHECK-LABEL: store_nd
3131
// CHECK-SAME: %[[ARG_0:.*]]: memref<24x32xf32>
32-
gpu.func @test_store_nd(%src: memref<24x32xf32>) {
32+
gpu.func @store_nd(%src: memref<24x32xf32>) {
3333
%tdesc = xegpu.create_nd_tdesc %src[0, 0] : memref<24x32xf32>
3434
-> !xegpu.tensor_desc<24x32xf32, #xegpu.layout<sg_layout = [4, 4], sg_data = [2, 2], lane_layout = [2, 2], lane_data = [1, 1]>>
3535
// CHECK-COUNT-12: xegpu.store_nd %{{.*}}, %{{.*}}
@@ -43,9 +43,9 @@ gpu.module @test_round_robin_assignment {
4343
gpu.return
4444
}
4545

46-
// CHECK-LABEL: test_update_nd
46+
// CHECK-LABEL: update_nd
4747
// CHECK-SAME: %[[ARG_0:.*]]: memref<24x32xf32>
48-
gpu.func @test_update_nd(%src: memref<24x32xf32>){
48+
gpu.func @update_nd(%src: memref<24x32xf32>){
4949
%tdesc = xegpu.create_nd_tdesc %src[0, 0] : memref<24x32xf32>
5050
-> !xegpu.tensor_desc<24x32xf32, #xegpu.layout<sg_layout = [4, 4], sg_data = [2, 2], lane_layout = [2, 2], lane_data = [1, 1]>>
5151
// CHECK-COUNT-12: xegpu.update_nd_offset %{{.*}}, [0, 16]
@@ -56,9 +56,9 @@ gpu.module @test_round_robin_assignment {
5656
gpu.return
5757
}
5858

59-
// CHECK-LABEL: test_dpas
59+
// CHECK-LABEL: dpas
6060
// CHECK-SAME: (%[[ARG_0:.*]]: memref<8x8xf32>, %[[ARG_1:.*]]: memref<8x8xf32>, %[[ARG_2:.*]]: memref<8x8xf32>)
61-
gpu.func @test_dpas(%a: memref<8x8xf32>, %b: memref<8x8xf32>, %c: memref<8x8xf32>) {
61+
gpu.func @dpas(%a: memref<8x8xf32>, %b: memref<8x8xf32>, %c: memref<8x8xf32>) {
6262
// CHECK-COUNT-4: xegpu.create_nd_tdesc %[[ARG_0]][%{{.*}}, %{{.*}}] : memref<8x8xf32>
6363
// CHECK-SAME-COUNT-4: -> !xegpu.tensor_desc<2x2xf32, #xegpu.layout<lane_layout = [2, 2], lane_data = [1, 1]>>
6464
// CHECK-NOT: xegpu.create_nd_tdesc
@@ -90,9 +90,9 @@ gpu.module @test_round_robin_assignment {
9090
gpu.return
9191
}
9292

93-
// CHECK-LABEL: test_prefetch_nd_tdesc
93+
// CHECK-LABEL: prefetch_nd_tdesc
9494
// CHECK-SAME: %[[ARG_0:.*]]: memref<24x32xf32>
95-
gpu.func @test_prefetch_nd_tdesc(%src: memref<24x32xf32>) {
95+
gpu.func @prefetch_nd_tdesc(%src: memref<24x32xf32>) {
9696
// CHECK-COUNT-12: xegpu.prefetch_nd %{{.*}}
9797
// CHECK-SAME-COUNT-12 : !xegpu.tensor_desc<2x2xf32, #xegpu.layout<lane_layout = [2, 2], lane_data = [1, 1]>>
9898
// CHECK-NOT: xegpu.prefetch_nd
@@ -103,7 +103,7 @@ gpu.module @test_round_robin_assignment {
103103
gpu.return
104104
}
105105

106-
gpu.func @test_scf_for(%arg0: memref<1024xf32>, %arg1: memref<1024xf32>) {
106+
gpu.func @scf_for(%arg0: memref<1024xf32>, %arg1: memref<1024xf32>) {
107107
%c1 = arith.constant 1 : index
108108
%c10 = arith.constant 10 : index
109109
%c0 = arith.constant 0 : index
@@ -126,7 +126,7 @@ gpu.module @test_round_robin_assignment {
126126
gpu.return
127127
}
128128

129-
gpu.func @test_scf_while_and_condition(%arg0: memref<1024xf32>, %arg1: memref<1024xf32>) {
129+
gpu.func @scf_while_and_condition(%arg0: memref<1024xf32>, %arg1: memref<1024xf32>) {
130130
%c1_i32 = arith.constant 1 : i32
131131
%c10_i32 = arith.constant 10 : i32
132132
%c0_i32 = arith.constant 0 : i32
@@ -150,7 +150,7 @@ gpu.module @test_round_robin_assignment {
150150
gpu.return
151151
}
152152

153-
gpu.func @test_scf_if(%arg0: memref<1024xf32>, %arg1: memref<1024xf32>) {
153+
gpu.func @scf_if(%arg0: memref<1024xf32>, %arg1: memref<1024xf32>) {
154154
%c10 = arith.constant 10 : index
155155
%0 = gpu.subgroup_id : index
156156
%1 = xegpu.create_nd_tdesc %arg0[0] : memref<1024xf32> -> !xegpu.tensor_desc<256xf32, #xegpu.layout<sg_layout = [8], sg_data = [16]>>
@@ -173,7 +173,7 @@ gpu.module @test_round_robin_assignment {
173173
gpu.return
174174
}
175175

176-
gpu.func @test_scf_if_tensor_desc(%arg0: memref<1024xf32>, %arg1: memref<1024xf32>) {
176+
gpu.func @scf_if_tensor_desc(%arg0: memref<1024xf32>, %arg1: memref<1024xf32>) {
177177
%c10 = arith.constant 10 : index
178178
%id = gpu.subgroup_id : index
179179

‎mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@
33
//CHECK: #map = affine_map<()[s0] -> (s0 floordiv 4)>
44
//CHECK: #map1 = affine_map<()[s0] -> (s0 mod 4)>
55
gpu.module @test_1_1_assignment {
6-
// CHECK-LABEL: test_create_nd_tdesc
6+
// CHECK-LABEL: create_nd_tdesc
77
// CHECK-SAME: %[[ARG_0:.*]]: memref<24x32xf32>
8-
gpu.func @test_create_nd_tdesc(%src: memref<24x32xf32>) {
8+
gpu.func @create_nd_tdesc(%src: memref<24x32xf32>) {
99
// CHECK: %[[SGID:.*]] = gpu.subgroup_id
1010
// CHECK: %[[C12:.*]] = arith.constant 12 : index
1111
// CHECK: %[[C4:.*]] = arith.constant 4 : index
@@ -30,9 +30,9 @@ gpu.module @test_1_1_assignment {
3030
gpu.return
3131
}
3232

33-
// CHECK-LABEL: test_load_nd_tdesc
33+
// CHECK-LABEL: load_nd_tdesc
3434
// CHECK-SAME: %[[ARG_0:.*]]: memref<24x32xf32>
35-
gpu.func @test_load_nd_tdesc(%src: memref<24x32xf32>) {
35+
gpu.func @load_nd_tdesc(%src: memref<24x32xf32>) {
3636
// CHECK: %[[TDESC:.*]] = xegpu.create_nd_tdesc %[[ARG_0]][{{%.*}}, {{%.*}}] : memref<24x32xf32>
3737
// CHECK-SAME: -> !xegpu.tensor_desc<12x8xf32, #xegpu.layout<lane_layout = [2, 8], lane_data = [1, 1]>>
3838
// CHECK: %[[LOAD:.*]] = xegpu.load_nd %[[TDESC]]
@@ -46,9 +46,9 @@ gpu.module @test_1_1_assignment {
4646
gpu.return
4747
}
4848

49-
// CHECK-LABEL: test_store_nd
49+
// CHECK-LABEL: store_nd
5050
// CHECK-SAME: %[[ARG_0:.*]]: memref<24x32xf32>
51-
gpu.func @test_store_nd(%src: memref<24x32xf32>) {
51+
gpu.func @store_nd(%src: memref<24x32xf32>) {
5252
// CHECK: %[[TDESC:.*]] = xegpu.create_nd_tdesc %[[ARG_0]][{{%.*}}, {{%.*}}] : memref<24x32xf32>
5353
// CHECK-SAME: -> !xegpu.tensor_desc<12x8xf32, #xegpu.layout<lane_layout = [2, 8], lane_data = [1, 1]>>
5454
// CHECK: %[[LOAD:.*]] = xegpu.load_nd %[[TDESC]]
@@ -66,9 +66,9 @@ gpu.module @test_1_1_assignment {
6666
gpu.return
6767
}
6868

69-
// CHECK-LABEL: test_update_nd
69+
// CHECK-LABEL: update_nd
7070
// CHECK-SAME: %[[ARG_0:.*]]: memref<24x32xf32>
71-
gpu.func @test_update_nd(%src: memref<24x32xf32>){
71+
gpu.func @update_nd(%src: memref<24x32xf32>){
7272
// CHECK: %[[TDESC:.*]] = xegpu.create_nd_tdesc %[[ARG_0]][{{%.*}}, {{%.*}}] : memref<24x32xf32>
7373
// CHECK-SAME: -> !xegpu.tensor_desc<12x8xf32, #xegpu.layout<lane_layout = [2, 8], lane_data = [1, 1]>>
7474
// CHECK: %[[UPDATE:.*]] = xegpu.update_nd_offset %[[TDESC]], [0, 16]
@@ -80,10 +80,10 @@ gpu.func @test_update_nd(%src: memref<24x32xf32>){
8080
gpu.return
8181
}
8282

83-
// CHECK-LABEL: test_dpas
83+
// CHECK-LABEL: dpas
8484
// CHECK-SAME: %[[ARG_0:.*]]: memref<24x32xf32>
8585
// CHECK-SAME: %[[ARG_1:.*]]: memref<32x24xf32>
86-
gpu.func @test_dpas(%a: memref<24x32xf32>, %b: memref<32x24xf32>) {
86+
gpu.func @dpas(%a: memref<24x32xf32>, %b: memref<32x24xf32>) {
8787
// CHECK: %[[TDESC_A:.*]] = xegpu.create_nd_tdesc %[[ARG_0]][{{%.*}}, {{%.*}}] : memref<24x32xf32>
8888
// CHECk-SAME: -> !xegpu.tensor_desc<12x8xf32, #xegpu.layout<lane_layout = [2, 8], lane_data = [1, 1]>>
8989
// CHECK: %[[LOAD_A:.*]] = xegpu.load_nd %[[TDESC_A]]
@@ -114,10 +114,10 @@ gpu.func @test_dpas(%a: memref<24x32xf32>, %b: memref<32x24xf32>) {
114114
}
115115

116116

117-
// CHECK-LABEL: test_dpas_no_sg_data
117+
// CHECK-LABEL: dpas_no_sg_data
118118
// CHECK-SAME: %[[ARG_0:.*]]: memref<24x32xf32>
119119
// CHECK-SAME: %[[ARG_1:.*]]: memref<32x24xf32>
120-
gpu.func @test_dpas_no_sg_data(%a: memref<24x32xf32>, %b: memref<32x24xf32>) {
120+
gpu.func @dpas_no_sg_data(%a: memref<24x32xf32>, %b: memref<32x24xf32>) {
121121
// CHECK: %[[TDESC_A:.*]] = xegpu.create_nd_tdesc %[[ARG_0]][{{%.*}}, {{%.*}}] : memref<24x32xf32>
122122
// CHECk-SAME: -> !xegpu.tensor_desc<12x8xf32, #xegpu.layout<lane_layout = [2, 8], lane_data = [1, 1]>>
123123
// CHECK: %[[LOAD_A:.*]] = xegpu.load_nd %[[TDESC_A]]
@@ -147,9 +147,9 @@ gpu.func @test_dpas_no_sg_data(%a: memref<24x32xf32>, %b: memref<32x24xf32>) {
147147
gpu.return
148148
}
149149

150-
// CHECK-LABEL: test_prefetch_nd_tdesc
150+
// CHECK-LABEL: prefetch_nd_tdesc
151151
// CHECK-SAME: %[[ARG_0:.*]]: memref<24x32xf32>
152-
gpu.func @test_prefetch_nd_tdesc(%src: memref<24x32xf32>) {
152+
gpu.func @prefetch_nd_tdesc(%src: memref<24x32xf32>) {
153153
// CHECK: %[[TDESC:.*]] = xegpu.create_nd_tdesc %[[ARG_0]][{{%.*}}, {{%.*}}] : memref<24x32xf32>
154154
// CHECK-SAME: -> !xegpu.tensor_desc<12x8xf32, #xegpu.layout<lane_layout = [2, 8], lane_data = [1, 1]>>
155155
// CHECK: xegpu.prefetch_nd %[[TDESC]]
@@ -161,16 +161,16 @@ gpu.func @test_dpas_no_sg_data(%a: memref<24x32xf32>, %b: memref<32x24xf32>) {
161161
gpu.return
162162
}
163163

164-
// CHECK-LABEL: test_dpas_with_no_create_nd_desc
165-
gpu.func @test_dpas_with_no_create_nd_desc(%a: vector<24x32xf32>, %b: vector<32x24xf32>) {
164+
// CHECK-LABEL: dpas_with_no_create_nd_desc
165+
gpu.func @dpas_with_no_create_nd_desc(%a: vector<24x32xf32>, %b: vector<32x24xf32>) {
166166
// CHECK-NOT: vector<12x12xf32>
167167
%dpas = xegpu.dpas %a, %b
168168
{layout = #xegpu.layout<sg_layout = [2, 2], sg_data = [12, 12], lane_layout = [2, 2], lane_data = [1, 1]>}
169169
: vector<24x32xf32>, vector<32x24xf32> -> vector<24x24xf32>
170170
gpu.return
171171
}
172172

173-
gpu.func @test_scf_for(%arg0: memref<1024x1024xf16>, %arg1: memref<1024x1024xf16>, %arg2: memref<1024x1024xf32>) {
173+
gpu.func @scf_for(%arg0: memref<1024x1024xf16>, %arg1: memref<1024x1024xf16>, %arg2: memref<1024x1024xf32>) {
174174
//CHECK: [[c0:%.+]] = arith.constant 0 : index
175175
//CHECK: [[c128:%.+]] = arith.constant 128 : index
176176
//CHECK: [[c1024:%.+]] = arith.constant 1024 : index
@@ -213,7 +213,7 @@ gpu.func @test_dpas_no_sg_data(%a: memref<24x32xf32>, %b: memref<32x24xf32>) {
213213
gpu.return
214214
}
215215

216-
gpu.func @test_scf_while_and_condition(%arg0: memref<1024xf32>, %arg1: memref<1024xf32>) {
216+
gpu.func @scf_while_and_condition(%arg0: memref<1024xf32>, %arg1: memref<1024xf32>) {
217217
%c1_i32 = arith.constant 1 : i32
218218
%c10_i32 = arith.constant 10 : i32
219219
%c0_i32 = arith.constant 0 : i32
@@ -238,7 +238,7 @@ gpu.func @test_dpas_no_sg_data(%a: memref<24x32xf32>, %b: memref<32x24xf32>) {
238238
gpu.return
239239
}
240240

241-
gpu.func @test_scf_if(%arg0: memref<1024xf32>, %arg1: memref<1024xf32>) {
241+
gpu.func @scf_if(%arg0: memref<1024xf32>, %arg1: memref<1024xf32>) {
242242
%c10 = arith.constant 10 : index
243243
%id = gpu.subgroup_id : index
244244

@@ -267,7 +267,7 @@ gpu.func @test_dpas_no_sg_data(%a: memref<24x32xf32>, %b: memref<32x24xf32>) {
267267
gpu.return
268268
}
269269

270-
gpu.func @test_scf_if_tensor_desc(%arg0: memref<1024xf32>, %arg1: memref<1024xf32>) {
270+
gpu.func @scf_if_tensor_desc(%arg0: memref<1024xf32>, %arg1: memref<1024xf32>) {
271271
%c10 = arith.constant 10 : index
272272
%id = gpu.subgroup_id : index
273273

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