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adam-yangarsenm
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[AMDGPU] Fixed llvm-debuginfo-analyzer for AMDGPU. (#145125)
Constructing Target triple with `ObjectFile::makeTriple` instead of just with `Arch` and leaving the rest unknown. Also creating the subtarget with the `CPU`. AMDGPU needs the full triple and `CPU` to disassemble correctly. To run a full test, also fixed a failure in `SIPreAllocateWWMRegs` with the `$noreg` operand in `DBG_VALUE`. --------- Co-authored-by: Matt Arsenault <[email protected]>
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-11
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7 files changed

+194
-11
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llvm/include/llvm/DebugInfo/LogicalView/Readers/LVBinaryReader.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -159,7 +159,8 @@ class LVBinaryReader : public LVReader {
159159
LVAddress WasmCodeSectionOffset = 0;
160160

161161
// Loads all info for the architecture of the provided object file.
162-
Error loadGenericTargetInfo(StringRef TheTriple, StringRef TheFeatures);
162+
Error loadGenericTargetInfo(StringRef TheTriple, StringRef TheFeatures,
163+
StringRef TheCPU);
163164

164165
virtual void mapRangeAddress(const object::ObjectFile &Obj) {}
165166
virtual void mapRangeAddress(const object::ObjectFile &Obj,

llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -275,7 +275,8 @@ void LVBinaryReader::mapVirtualAddress(const object::COFFObjectFile &COFFObj) {
275275
}
276276

277277
Error LVBinaryReader::loadGenericTargetInfo(StringRef TheTriple,
278-
StringRef TheFeatures) {
278+
StringRef TheFeatures,
279+
StringRef TheCPU) {
279280
std::string TargetLookupError;
280281
const Target *TheTarget =
281282
TargetRegistry::lookupTarget(TheTriple, TargetLookupError);
@@ -298,9 +299,8 @@ Error LVBinaryReader::loadGenericTargetInfo(StringRef TheTriple,
298299
MAI.reset(AsmInfo);
299300

300301
// Target subtargets.
301-
StringRef CPU;
302302
MCSubtargetInfo *SubtargetInfo(
303-
TheTarget->createMCSubtargetInfo(TheTriple, CPU, TheFeatures));
303+
TheTarget->createMCSubtargetInfo(TheTriple, TheCPU, TheFeatures));
304304
if (!SubtargetInfo)
305305
return createStringError(errc::invalid_argument,
306306
"no subtarget info for target " + TheTriple);

llvm/lib/DebugInfo/LogicalView/Readers/LVCodeViewReader.cpp

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1190,7 +1190,12 @@ Error LVCodeViewReader::loadTargetInfo(const ObjectFile &Obj) {
11901190
FeaturesValue = SubtargetFeatures();
11911191
}
11921192
FeaturesValue = *Features;
1193-
return loadGenericTargetInfo(TT.str(), FeaturesValue.getString());
1193+
1194+
StringRef CPU;
1195+
if (auto OptCPU = Obj.tryGetCPUName())
1196+
CPU = *OptCPU;
1197+
1198+
return loadGenericTargetInfo(TT.str(), FeaturesValue.getString(), CPU);
11941199
}
11951200

11961201
Error LVCodeViewReader::loadTargetInfo(const PDBFile &Pdb) {
@@ -1200,8 +1205,9 @@ Error LVCodeViewReader::loadTargetInfo(const PDBFile &Pdb) {
12001205
TT.setOS(Triple::Win32);
12011206

12021207
StringRef TheFeature = "";
1208+
StringRef TheCPU = "";
12031209

1204-
return loadGenericTargetInfo(TT.str(), TheFeature);
1210+
return loadGenericTargetInfo(TT.str(), TheFeature, TheCPU);
12051211
}
12061212

12071213
std::string LVCodeViewReader::getRegisterName(LVSmall Opcode,

llvm/lib/DebugInfo/LogicalView/Readers/LVDWARFReader.cpp

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -956,10 +956,7 @@ LVElement *LVDWARFReader::getElementForOffset(LVOffset Offset,
956956
Error LVDWARFReader::loadTargetInfo(const ObjectFile &Obj) {
957957
// Detect the architecture from the object file. We usually don't need OS
958958
// info to lookup a target and create register info.
959-
Triple TT;
960-
TT.setArch(Triple::ArchType(Obj.getArch()));
961-
TT.setVendor(Triple::UnknownVendor);
962-
TT.setOS(Triple::UnknownOS);
959+
Triple TT = Obj.makeTriple();
963960

964961
// Features to be passed to target/subtarget
965962
Expected<SubtargetFeatures> Features = Obj.getFeatures();
@@ -969,7 +966,12 @@ Error LVDWARFReader::loadTargetInfo(const ObjectFile &Obj) {
969966
FeaturesValue = SubtargetFeatures();
970967
}
971968
FeaturesValue = *Features;
972-
return loadGenericTargetInfo(TT.str(), FeaturesValue.getString());
969+
970+
StringRef CPU;
971+
if (auto OptCPU = Obj.tryGetCPUName())
972+
CPU = *OptCPU;
973+
974+
return loadGenericTargetInfo(TT.str(), FeaturesValue.getString(), CPU);
973975
}
974976

975977
void LVDWARFReader::mapRangeAddress(const ObjectFile &Obj) {

llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -130,6 +130,9 @@ void SIPreAllocateWWMRegs::rewriteRegs(MachineFunction &MF) {
130130
if (VirtReg.isPhysical())
131131
continue;
132132

133+
if (!VirtReg.isValid())
134+
continue;
135+
133136
if (!VRM->hasPhys(VirtReg))
134137
continue;
135138

Lines changed: 100 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,100 @@
1+
; RUN: llc %s -o %t.o -mcpu=gfx1030 -filetype=obj -O0
2+
; RUN: llvm-debuginfo-analyzer %t.o --print=all --attribute=all | FileCheck %s
3+
4+
; This test compiles this module with AMDGPU backend under -O0,
5+
; and makes sure llvm-debuginfo-analyzer works for it.
6+
7+
; Simple checks to make sure llvm-debuginfo-analzyer didn't fail early.
8+
; CHECK: Logical View:
9+
; CHECK: {CompileUnit}
10+
; CHECK-DAG: {Parameter} 'dtid' -> [0x{{[a-f0-9]+}}]'uint3'
11+
; CHECK-DAG: {Variable} 'my_var2' -> [0x{{[a-f0-9]+}}]'float'
12+
; CHECK-DAG: {Line} {{.+}}basic_var.hlsl
13+
; CHECK: {Code} 's_endpgm'
14+
15+
source_filename = "module"
16+
target triple = "amdgcn-amd-amdpal"
17+
18+
%dx.types.ResRet.f32 = type { float, float, float, float, i32 }
19+
20+
define dllexport amdgpu_cs void @_amdgpu_cs_main(i32 inreg noundef %globalTable, i32 inreg noundef %userdata4, <3 x i32> inreg noundef %WorkgroupId, i32 inreg noundef %MultiDispatchInfo, <3 x i32> noundef %LocalInvocationId) #0 !dbg !14 {
21+
%LocalInvocationId.i0 = extractelement <3 x i32> %LocalInvocationId, i64 0, !dbg !28
22+
%WorkgroupId.i0 = extractelement <3 x i32> %WorkgroupId, i64 0, !dbg !28
23+
%pc = call i64 @llvm.amdgcn.s.getpc(), !dbg !28
24+
%offset = shl i32 %WorkgroupId.i0, 6, !dbg !28
25+
%dtid = add i32 %LocalInvocationId.i0, %offset, !dbg !28
26+
#dbg_value(i32 %dtid, !29, !DIExpression(DW_OP_LLVM_fragment, 0, 32), !28)
27+
%pc_hi = and i64 %pc, -4294967296, !dbg !30
28+
%zext = zext i32 %userdata4 to i64, !dbg !30
29+
%ptr_val = or disjoint i64 %pc_hi, %zext, !dbg !30
30+
%ptr = inttoptr i64 %ptr_val to ptr addrspace(4), !dbg !30
31+
call void @llvm.assume(i1 true) [ "align"(ptr addrspace(4) %ptr, i32 4), "dereferenceable"(ptr addrspace(4) %ptr, i32 -1) ], !dbg !30
32+
%uav_0 = load <4 x i32>, ptr addrspace(4) %ptr, align 4, !dbg !30, !invariant.load !2
33+
%uav_load_1 = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %uav_0, i32 %dtid, i32 0, i32 0, i32 0), !dbg !30
34+
#dbg_value(%dx.types.ResRet.f32 poison, !31, !DIExpression(), !32)
35+
%mul = fmul reassoc arcp contract afn float %uav_load_1, 2.000000e+00, !dbg !33
36+
#dbg_value(float %mul, !34, !DIExpression(), !35)
37+
call void @llvm.assume(i1 true) [ "align"(ptr addrspace(4) %ptr, i32 4), "dereferenceable"(ptr addrspace(4) %ptr, i32 -1) ], !dbg !36
38+
%uav_1_ptr = getelementptr i8, ptr addrspace(4) %ptr, i64 32, !dbg !36
39+
%.upto01 = insertelement <4 x float> poison, float %mul, i64 0, !dbg !36
40+
%filled_vector = shufflevector <4 x float> %.upto01, <4 x float> poison, <4 x i32> zeroinitializer, !dbg !36
41+
%uav_1 = load <4 x i32>, ptr addrspace(4) %uav_1_ptr, align 4, !dbg !36, !invariant.load !2
42+
call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %filled_vector, <4 x i32> %uav_1, i32 %dtid, i32 0, i32 0, i32 0), !dbg !36
43+
ret void, !dbg !37
44+
}
45+
46+
declare noundef i64 @llvm.amdgcn.s.getpc() #1
47+
48+
declare void @llvm.assume(i1 noundef) #2
49+
50+
declare void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float>, <4 x i32>, i32, i32, i32, i32 immarg) #3
51+
52+
declare float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32>, i32, i32, i32, i32 immarg) #4
53+
54+
attributes #0 = { memory(readwrite) }
55+
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
56+
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
57+
attributes #3 = { nocallback nofree nosync nounwind willreturn memory(write) }
58+
attributes #4 = { nocallback nofree nosync nounwind willreturn memory(read) }
59+
60+
!llvm.dbg.cu = !{!0}
61+
!llvm.module.flags = !{!12, !13}
62+
63+
!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "dxcoob 1.7.2308.16 (52da17e29)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, globals: !3)
64+
!1 = !DIFile(filename: "tests\\basic_var.hlsl", directory: "")
65+
!2 = !{}
66+
!3 = !{!4, !10}
67+
!4 = distinct !DIGlobalVariableExpression(var: !5, expr: !DIExpression())
68+
!5 = !DIGlobalVariable(name: "u0", linkageName: "\01?u0@@3V?$RWBuffer@M@@A", scope: !0, file: !1, line: 2, type: !6, isLocal: false, isDefinition: true)
69+
!6 = !DICompositeType(tag: DW_TAG_class_type, name: "RWBuffer<float>", file: !1, line: 2, size: 32, align: 32, elements: !2, templateParams: !7)
70+
!7 = !{!8}
71+
!8 = !DITemplateTypeParameter(name: "element", type: !9)
72+
!9 = !DIBasicType(name: "float", size: 32, align: 32, encoding: DW_ATE_float)
73+
!10 = distinct !DIGlobalVariableExpression(var: !11, expr: !DIExpression())
74+
!11 = !DIGlobalVariable(name: "u1", linkageName: "\01?u1@@3V?$RWBuffer@M@@A", scope: !0, file: !1, line: 3, type: !6, isLocal: false, isDefinition: true)
75+
!12 = !{i32 2, !"Dwarf Version", i32 5}
76+
!13 = !{i32 2, !"Debug Info Version", i32 3}
77+
!14 = distinct !DISubprogram(name: "main", scope: !1, file: !1, line: 7, type: !15, scopeLine: 7, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0)
78+
!15 = !DISubroutineType(types: !16)
79+
!16 = !{null, !17}
80+
!17 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint3", file: !1, baseType: !18)
81+
!18 = !DICompositeType(tag: DW_TAG_class_type, name: "vector<unsigned int, 3>", file: !1, size: 96, align: 32, elements: !19, templateParams: !24)
82+
!19 = !{!20, !22, !23}
83+
!20 = !DIDerivedType(tag: DW_TAG_member, name: "x", scope: !18, file: !1, baseType: !21, size: 32, align: 32, flags: DIFlagPublic)
84+
!21 = !DIBasicType(name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
85+
!22 = !DIDerivedType(tag: DW_TAG_member, name: "y", scope: !18, file: !1, baseType: !21, size: 32, align: 32, offset: 32, flags: DIFlagPublic)
86+
!23 = !DIDerivedType(tag: DW_TAG_member, name: "z", scope: !18, file: !1, baseType: !21, size: 32, align: 32, offset: 64, flags: DIFlagPublic)
87+
!24 = !{!25, !26}
88+
!25 = !DITemplateTypeParameter(name: "element", type: !21)
89+
!26 = !DITemplateValueParameter(name: "element_count", type: !27, value: i32 3)
90+
!27 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
91+
!28 = !DILocation(line: 7, column: 17, scope: !14)
92+
!29 = !DILocalVariable(name: "dtid", arg: 1, scope: !14, file: !1, line: 7, type: !17)
93+
!30 = !DILocation(line: 11, column: 18, scope: !14)
94+
!31 = !DILocalVariable(name: "my_var", scope: !14, file: !1, line: 11, type: !9)
95+
!32 = !DILocation(line: 11, column: 9, scope: !14)
96+
!33 = !DILocation(line: 14, column: 26, scope: !14)
97+
!34 = !DILocalVariable(name: "my_var2", scope: !14, file: !1, line: 14, type: !9)
98+
!35 = !DILocation(line: 14, column: 9, scope: !14)
99+
!36 = !DILocation(line: 17, column: 14, scope: !14)
100+
!37 = !DILocation(line: 19, column: 1, scope: !14)
Lines changed: 71 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,71 @@
1+
# RUN: llc %s -o - -mcpu=gfx1030 -O0 -run-pass=si-pre-allocate-wwm-regs | FileCheck %s
2+
3+
# Simple regression test to make sure DBG_VALUE $noreg does not assert in the pass
4+
5+
# CHECK: $vgpr0 = IMPLICIT_DEF
6+
# CHECK: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr3, 0, $vgpr0
7+
8+
--- |
9+
target triple = "amdgcn-amd-amdpal"
10+
%dx.types.ResRet.f32 = type { float, float, float, float, i32 }
11+
12+
define dllexport amdgpu_cs void @_amdgpu_cs_main(i32 inreg noundef %globalTable, i32 inreg noundef %userdata4, <3 x i32> inreg noundef %WorkgroupId, i32 inreg noundef %MultiDispatchInfo, <3 x i32> noundef %LocalInvocationId) #0 !dbg !5 {
13+
#dbg_value(i32 poison, !19, !DIExpression(DW_OP_LLVM_fragment, 0, 32), !20)
14+
#dbg_value(%dx.types.ResRet.f32 poison, !21, !DIExpression(), !23)
15+
ret void, !dbg !24
16+
}
17+
18+
attributes #0 = { memory(readwrite) "amdgpu-prealloc-sgpr-spill-vgprs" }
19+
20+
!llvm.dbg.cu = !{!0}
21+
!llvm.module.flags = !{!3, !4}
22+
23+
!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "dxcoob 1.7.2308.16 (52da17e29)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, globals: !2)
24+
!1 = !DIFile(filename: "tests\\basic_var.hlsl", directory: "")
25+
!2 = !{}
26+
!3 = !{i32 2, !"Dwarf Version", i32 5}
27+
!4 = !{i32 2, !"Debug Info Version", i32 3}
28+
!5 = distinct !DISubprogram(name: "main", scope: !1, file: !1, line: 7, type: !6, scopeLine: 7, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0)
29+
!6 = !DISubroutineType(types: !7)
30+
!7 = !{null, !8}
31+
!8 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint3", file: !1, baseType: !9)
32+
!9 = !DICompositeType(tag: DW_TAG_class_type, name: "vector<unsigned int, 3>", file: !1, size: 96, align: 32, elements: !10, templateParams: !15)
33+
!10 = !{!11, !13, !14}
34+
!11 = !DIDerivedType(tag: DW_TAG_member, name: "x", scope: !9, file: !1, baseType: !12, size: 32, align: 32, flags: DIFlagPublic)
35+
!12 = !DIBasicType(name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
36+
!13 = !DIDerivedType(tag: DW_TAG_member, name: "y", scope: !9, file: !1, baseType: !12, size: 32, align: 32, offset: 32, flags: DIFlagPublic)
37+
!14 = !DIDerivedType(tag: DW_TAG_member, name: "z", scope: !9, file: !1, baseType: !12, size: 32, align: 32, offset: 64, flags: DIFlagPublic)
38+
!15 = !{!16, !17}
39+
!16 = !DITemplateTypeParameter(name: "element", type: !12)
40+
!17 = !DITemplateValueParameter(name: "element_count", type: !18, value: i32 3)
41+
!18 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
42+
!19 = !DILocalVariable(name: "dtid", arg: 1, scope: !5, file: !1, line: 7, type: !8)
43+
!20 = !DILocation(line: 7, column: 17, scope: !5)
44+
!21 = !DILocalVariable(name: "my_var", scope: !5, file: !1, line: 11, type: !22)
45+
!22 = !DIBasicType(name: "float", size: 32, align: 32, encoding: DW_ATE_float)
46+
!23 = !DILocation(line: 11, column: 9, scope: !5)
47+
!24 = !DILocation(line: 19, column: 1, scope: !5)
48+
...
49+
---
50+
name: _amdgpu_cs_main
51+
tracksRegLiveness: true
52+
machineFunctionInfo:
53+
isEntryFunction: true
54+
hasSpilledSGPRs: true
55+
stackPtrOffsetReg: '$sgpr32'
56+
occupancy: 16
57+
sgprForEXECCopy: '$sgpr12_sgpr13'
58+
body: |
59+
bb.0 (%ir-block.0):
60+
liveins: $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2
61+
62+
%0:vgpr_32 = IMPLICIT_DEF
63+
%2:vgpr_32 = IMPLICIT_DEF
64+
%2:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr3, 0, %2
65+
renamable $sgpr3 = COPY killed $sgpr2
66+
renamable $sgpr4 = S_MOV_B32 6
67+
%3:vgpr_32 = V_LSHL_ADD_U32_e64 killed $sgpr3, killed $sgpr4, %0, implicit $exec
68+
DBG_VALUE %3, $noreg, !19, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !20
69+
DBG_VALUE $noreg, $noreg, !21, !DIExpression(), debug-location !23
70+
S_ENDPGM 0
71+
...

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