[RISCV][Sema] Add feature check for target attribute to VSETVL intrinsics (#126064)

This fixes the target attribute issue for vsetvl and vsetvlmax
intrinsics.
Fixes #125154

Author: 4vtomat

clang/include/clang/Basic/riscv_vector.td

@@ -634,7 +634,6 @@ let HeaderCode =
 #define __riscv_vsetvl_e32m4(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 2)
 #define __riscv_vsetvl_e32m8(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 3)
 
-#if __riscv_v_elen >= 64
 #define __riscv_vsetvl_e8mf8(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 5)
 #define __riscv_vsetvl_e16mf4(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 6)
 #define __riscv_vsetvl_e32mf2(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 7)
@@ -643,7 +642,6 @@ let HeaderCode =
 #define __riscv_vsetvl_e64m2(avl) __builtin_rvv_vsetvli((size_t)(avl), 3, 1)
 #define __riscv_vsetvl_e64m4(avl) __builtin_rvv_vsetvli((size_t)(avl), 3, 2)
 #define __riscv_vsetvl_e64m8(avl) __builtin_rvv_vsetvli((size_t)(avl), 3, 3)
-#endif
 
 #define __riscv_vsetvlmax_e8mf4() __builtin_rvv_vsetvlimax(0, 6)
 #define __riscv_vsetvlmax_e8mf2() __builtin_rvv_vsetvlimax(0, 7)
@@ -663,7 +661,6 @@ let HeaderCode =
 #define __riscv_vsetvlmax_e32m4() __builtin_rvv_vsetvlimax(2, 2)
 #define __riscv_vsetvlmax_e32m8() __builtin_rvv_vsetvlimax(2, 3)
 
-#if __riscv_v_elen >= 64
 #define __riscv_vsetvlmax_e8mf8() __builtin_rvv_vsetvlimax(0, 5)
 #define __riscv_vsetvlmax_e16mf4() __builtin_rvv_vsetvlimax(1, 6)
 #define __riscv_vsetvlmax_e32mf2() __builtin_rvv_vsetvlimax(2, 7)
@@ -672,7 +669,6 @@ let HeaderCode =
 #define __riscv_vsetvlmax_e64m2() __builtin_rvv_vsetvlimax(3, 1)
 #define __riscv_vsetvlmax_e64m4() __builtin_rvv_vsetvlimax(3, 2)
 #define __riscv_vsetvlmax_e64m8() __builtin_rvv_vsetvlimax(3, 3)
-#endif
 
 }] in
 def vsetvl_macro: RVVHeader;

clang/lib/Sema/SemaRISCV.cpp

@@ -624,13 +624,34 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI,
   }
   }
 
+  auto CheckVSetVL = [&](unsigned SEWOffset, unsigned LMULOffset) -> bool {
+    const FunctionDecl *FD = SemaRef.getCurFunctionDecl();
+    llvm::StringMap<bool> FunctionFeatureMap;
+    Context.getFunctionFeatureMap(FunctionFeatureMap, FD);
+    llvm::APSInt SEWResult;
+    llvm::APSInt LMULResult;
+    if (SemaRef.BuiltinConstantArg(TheCall, SEWOffset, SEWResult) ||
+        SemaRef.BuiltinConstantArg(TheCall, LMULOffset, LMULResult))
+      return true;
+    int SEWValue = SEWResult.getSExtValue();
+    int LMULValue = LMULResult.getSExtValue();
+    if (((SEWValue == 0 && LMULValue == 5) || // e8mf8
+         (SEWValue == 1 && LMULValue == 6) || // e16mf4
+         (SEWValue == 2 && LMULValue == 7) || // e32mf2
+         SEWValue == 3) &&                    // e64
+        !TI.hasFeature("zve64x") &&
+        !FunctionFeatureMap.lookup("zve64x"))
+      return Diag(TheCall->getBeginLoc(),
+                  diag::err_riscv_builtin_requires_extension)
+             << /* IsExtension */ true << TheCall->getSourceRange() << "zve64x";
+    return SemaRef.BuiltinConstantArgRange(TheCall, SEWOffset, 0, 3) ||
+           CheckLMUL(TheCall, LMULOffset);
+  };
   switch (BuiltinID) {
   case RISCVVector::BI__builtin_rvv_vsetvli:
-    return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 3) ||
-           CheckLMUL(TheCall, 2);
+    return CheckVSetVL(1, 2);
   case RISCVVector::BI__builtin_rvv_vsetvlimax:
-    return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 3) ||
-           CheckLMUL(TheCall, 1);
+    return CheckVSetVL(0, 1);
   case RISCVVector::BI__builtin_rvv_vget_v: {
     ASTContext::BuiltinVectorTypeInfo ResVecInfo =
         Context.getBuiltinVectorTypeInfo(cast<BuiltinType>(

clang/test/CodeGen/RISCV/riscv-func-attr-target.c

@@ -65,6 +65,20 @@ void test_rvv_f64_type_w_zve64d() {
   vfloat64m1_t v;
 }
 
+__attribute__((target("arch=+v")))
+int test_vsetvl_e64m1(unsigned avl) {
+// CHECK-LABEL: test_vsetvl_e64m1
+// CHECK-SAME: #13
+    return __riscv_vsetvl_e64m1(avl);
+}
+
+__attribute__((target("arch=+v")))
+int test_vsetvlmax_e64m1() {
+// CHECK-LABEL: test_vsetvlmax_e64m1
+// CHECK-SAME: #13
+    return __riscv_vsetvlmax_e64m1();
+}
+
 //.
 // CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zifencei,+zmmul,-relax,-zbb,-zfa" }
 // CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" }