Skip to content

Commit 8783bd5

Browse files
authored
[LLVM][TableGen] Change CodeGenInstAlias to use const Record pointers (#108753)
Change CodeGenInstAlias to use const Record pointers. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
1 parent f4763b3 commit 8783bd5

File tree

4 files changed

+22
-19
lines changed

4 files changed

+22
-19
lines changed

llvm/utils/TableGen/AsmMatcherEmitter.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -454,7 +454,7 @@ struct MatchableInfo {
454454
int64_t ImmVal;
455455

456456
/// Register - This is the register record.
457-
Record *Register;
457+
const Record *Register;
458458
};
459459

460460
/// MINumOperands - The number of MCInst operands populated by this
@@ -486,7 +486,7 @@ struct MatchableInfo {
486486
return X;
487487
}
488488

489-
static ResOperand getRegOp(Record *Reg) {
489+
static ResOperand getRegOp(const Record *Reg) {
490490
ResOperand X;
491491
X.Kind = RegOperand;
492492
X.Register = Reg;
@@ -1946,7 +1946,7 @@ void MatchableInfo::buildAliasResultOperands(bool AliasConstraintsAreChecked) {
19461946
break;
19471947
}
19481948
case CodeGenInstAlias::ResultOperand::K_Reg: {
1949-
Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1949+
const Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
19501950
ResOperands.push_back(ResOperand::getRegOp(Reg));
19511951
break;
19521952
}

llvm/utils/TableGen/AsmWriterEmitter.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -953,7 +953,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
953953
if (Rec->isSubClassOf("RegisterClass")) {
954954
if (!IAP.isOpMapped(ROName)) {
955955
IAP.addOperand(ROName, MIOpNum, PrintMethodIdx);
956-
Record *R = CGA.ResultOperands[i].getRecord();
956+
const Record *R = CGA.ResultOperands[i].getRecord();
957957
if (R->isSubClassOf("RegisterOperand"))
958958
R = R->getValueAsDef("RegClass");
959959
IAP.addCond(std::string(

llvm/utils/TableGen/Common/CodeGenInstAlias.cpp

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -24,9 +24,11 @@ using namespace llvm;
2424
/// constructor. It checks if an argument in an InstAlias pattern matches
2525
/// the corresponding operand of the instruction. It returns true on a
2626
/// successful match, with ResOp set to the result operand to be used.
27-
bool CodeGenInstAlias::tryAliasOpMatch(DagInit *Result, unsigned AliasOpNo,
27+
bool CodeGenInstAlias::tryAliasOpMatch(const DagInit *Result,
28+
unsigned AliasOpNo,
2829
const Record *InstOpRec, bool hasSubOps,
29-
ArrayRef<SMLoc> Loc, CodeGenTarget &T,
30+
ArrayRef<SMLoc> Loc,
31+
const CodeGenTarget &T,
3032
ResultOperand &ResOp) {
3133
Init *Arg = Result->getArg(AliasOpNo);
3234
DefInit *ADI = dyn_cast<DefInit>(Arg);
@@ -152,11 +154,11 @@ unsigned CodeGenInstAlias::ResultOperand::getMINumOperands() const {
152154
if (!isRecord())
153155
return 1;
154156

155-
Record *Rec = getRecord();
157+
const Record *Rec = getRecord();
156158
if (!Rec->isSubClassOf("Operand"))
157159
return 1;
158160

159-
DagInit *MIOpInfo = Rec->getValueAsDag("MIOperandInfo");
161+
const DagInit *MIOpInfo = Rec->getValueAsDag("MIOperandInfo");
160162
if (MIOpInfo->getNumArgs() == 0) {
161163
// Unspecified, so it defaults to 1
162164
return 1;
@@ -165,7 +167,8 @@ unsigned CodeGenInstAlias::ResultOperand::getMINumOperands() const {
165167
return MIOpInfo->getNumArgs();
166168
}
167169

168-
CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) {
170+
CodeGenInstAlias::CodeGenInstAlias(const Record *R, const CodeGenTarget &T)
171+
: TheDef(R) {
169172
Result = R->getValueAsDag("ResultInst");
170173
AsmString = std::string(R->getValueAsString("AsmString"));
171174

llvm/utils/TableGen/Common/CodeGenInstAlias.h

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ class Record;
3232
/// CodeGenInstAlias - This represents an InstAlias definition.
3333
class CodeGenInstAlias {
3434
public:
35-
Record *TheDef; // The actual record defining this InstAlias.
35+
const Record *TheDef; // The actual record defining this InstAlias.
3636

3737
/// AsmString - The format string used to emit a .s file for the
3838
/// instruction.
@@ -48,16 +48,16 @@ class CodeGenInstAlias {
4848
struct ResultOperand {
4949
private:
5050
std::string Name;
51-
Record *R = nullptr;
51+
const Record *R = nullptr;
5252
int64_t Imm = 0;
5353

5454
public:
5555
enum { K_Record, K_Imm, K_Reg } Kind;
5656

57-
ResultOperand(std::string N, Record *r)
58-
: Name(std::move(N)), R(r), Kind(K_Record) {}
57+
ResultOperand(std::string N, const Record *R)
58+
: Name(std::move(N)), R(R), Kind(K_Record) {}
5959
ResultOperand(int64_t I) : Imm(I), Kind(K_Imm) {}
60-
ResultOperand(Record *r) : R(r), Kind(K_Reg) {}
60+
ResultOperand(Record *R) : R(R), Kind(K_Reg) {}
6161

6262
bool isRecord() const { return Kind == K_Record; }
6363
bool isImm() const { return Kind == K_Imm; }
@@ -67,15 +67,15 @@ class CodeGenInstAlias {
6767
assert(isRecord());
6868
return Name;
6969
}
70-
Record *getRecord() const {
70+
const Record *getRecord() const {
7171
assert(isRecord());
7272
return R;
7373
}
7474
int64_t getImm() const {
7575
assert(isImm());
7676
return Imm;
7777
}
78-
Record *getRegister() const {
78+
const Record *getRegister() const {
7979
assert(isReg());
8080
return R;
8181
}
@@ -93,11 +93,11 @@ class CodeGenInstAlias {
9393
/// of them are matched by the operand, the second value should be -1.
9494
std::vector<std::pair<unsigned, int>> ResultInstOperandIndex;
9595

96-
CodeGenInstAlias(Record *R, CodeGenTarget &T);
96+
CodeGenInstAlias(const Record *R, const CodeGenTarget &T);
9797

98-
bool tryAliasOpMatch(DagInit *Result, unsigned AliasOpNo,
98+
bool tryAliasOpMatch(const DagInit *Result, unsigned AliasOpNo,
9999
const Record *InstOpRec, bool hasSubOps,
100-
ArrayRef<SMLoc> Loc, CodeGenTarget &T,
100+
ArrayRef<SMLoc> Loc, const CodeGenTarget &T,
101101
ResultOperand &ResOp);
102102
};
103103

0 commit comments

Comments
 (0)