[MIPS]Optimize ((signext (xor (trunc X), imm)) to (xor (signext_inreg X, i32), imm)

The constant operand of the XOR is an i32, which makes the two operands
being truncated to i32, and sign extended to i64 afterwards. Since both
of the i32 operands are sign extended to i64 before performing the
TRUNCATE operation, we just remove the unnecessary TRUNCATE and
SIGN_EXTEND.

Fix #99783

Author: anbbna

llvm/lib/Target/Mips/MipsISelLowering.cpp

@@ -521,7 +521,8 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
   setOperationAction(ISD::TRAP, MVT::Other, Legal);
 
   setTargetDAGCombine({ISD::SDIVREM, ISD::UDIVREM, ISD::SELECT, ISD::AND,
-                       ISD::OR, ISD::ADD, ISD::SUB, ISD::AssertZext, ISD::SHL});
+                       ISD::OR, ISD::ADD, ISD::SUB, ISD::AssertZext, ISD::SHL,
+                       ISD::SIGN_EXTEND});
 
   if (Subtarget.isGP64bit())
     setMaxAtomicSizeInBitsSupported(64);
@@ -1221,6 +1222,43 @@ static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
                      DAG.getConstant(SMSize, DL, MVT::i32));
 }
 
+static SDValue performSignExtendCombine(SDNode *N, SelectionDAG &DAG,
+                                        TargetLowering::DAGCombinerInfo &DCI,
+                                        const MipsSubtarget &Subtarget) {
+  if (DCI.Level != AfterLegalizeDAG || !Subtarget.isGP64bit()) {
+    return SDValue();
+  }
+
+  SDValue N0 = N->getOperand(0);
+  EVT VT = N->getValueType(0);
+
+  // Pattern match XOR.
+  // $dst = (sign_extend (xor (trunc $src, i32), imm), i64)
+  // => $dst = (xor (signext_inreg $src, i32), imm as i64)
+  if (N0.getOpcode() == ISD::XOR &&
+      N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
+      N0.getOperand(1).getOpcode() == ISD::Constant) {
+    SDValue TruncateSource = N0.getOperand(0).getOperand(0);
+    auto *ConstantOperand = dyn_cast<ConstantSDNode>(N0->getOperand(1));
+
+    // Remove the unnecessary truncate + signext, and perform the operation
+    // using the initial sign-extended i64 values, with the constant also sign
+    // extended to i64. Note: ConstImm is either passed as a 32-bit immediate to
+    // xori, or gets "assembled" to anoter register and a xor is emitted, if
+    // ConstImm can't fit in 32 bits.
+    if (VT == MVT::i64 && VT == TruncateSource.getValueType()) {
+      SDValue FirstOperand =
+          DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N0), VT, TruncateSource,
+                      DAG.getValueType(MVT::i32));
+      APInt ConstImm(64, ConstantOperand->getSExtValue(), true);
+      return DAG.getNode(ISD::XOR, SDLoc(N0), VT, FirstOperand,
+                         DAG.getConstant(ConstImm, SDLoc(N0), VT));
+    }
+  }
+
+  return SDValue();
+}
+
 SDValue  MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
   const {
   SelectionDAG &DAG = DCI.DAG;
@@ -1246,6 +1284,8 @@ SDValue  MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
     return performSHLCombine(N, DAG, DCI, Subtarget);
   case ISD::SUB:
     return performSUBCombine(N, DAG, DCI, Subtarget);
+  case ISD::SIGN_EXTEND:
+    return performSignExtendCombine(N, DAG, DCI, Subtarget);
   }
 
   return SDValue();