[AArch64] Use i32 extract from UADDV in popcount lowering.

We need the top bits to be zeroes, but an v8i8->i32 EXTRACT_VECTOR_ELT will
anyext into the top bits. The instruction we create (UADDV) is known to be
zeroes in the upper bits, so we can convert to a larger v2i32 vector and
extract from there, similar to the operation currently performed for i64 types.

Author: davemgreen

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -10852,13 +10852,10 @@ SDValue AArch64TargetLowering::LowerCTPOP_PARITY(SDValue Op,
 
     SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
     SDValue AddV = DAG.getNode(AArch64ISD::UADDV, DL, MVT::v8i8, CtPop);
-    if (VT == MVT::i32)
-      AddV = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, AddV,
-                         DAG.getConstant(0, DL, MVT::i64));
-    else
-      AddV = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
-                         DAG.getNode(AArch64ISD::NVCAST, DL, MVT::v1i64, AddV),
-                         DAG.getConstant(0, DL, MVT::i64));
+    AddV = DAG.getNode(AArch64ISD::NVCAST, DL,
+                       VT == MVT::i32 ? MVT::v2i32 : MVT::v1i64, AddV);
+    AddV = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, AddV,
+                       DAG.getConstant(0, DL, MVT::i64));
     if (IsParity)
       AddV = DAG.getNode(ISD::AND, DL, VT, AddV, DAG.getConstant(1, DL, VT));
     return AddV;

llvm/test/CodeGen/AArch64/popcount.ll

@@ -686,7 +686,7 @@ define i32 @ctpop_into_extract(ptr %p) {
 ; CHECK-NEXT:    fmov s1, w9
 ; CHECK-NEXT:    cnt v1.8b, v1.8b
 ; CHECK-NEXT:    addv b1, v1.8b
-; CHECK-NEXT:    mov v2.b[4], v1.b[0]
+; CHECK-NEXT:    mov v2.s[1], v1.s[0]
 ; CHECK-NEXT:    sub v0.2s, v0.2s, v2.2s
 ; CHECK-NEXT:    str d0, [x8]
 ; CHECK-NEXT:    ret
@@ -701,7 +701,7 @@ define i32 @ctpop_into_extract(ptr %p) {
 ; BE-NEXT:    fmov s1, w9
 ; BE-NEXT:    cnt v1.8b, v1.8b
 ; BE-NEXT:    addv b1, v1.8b
-; BE-NEXT:    mov v2.b[4], v1.b[0]
+; BE-NEXT:    mov v2.s[1], v1.s[0]
 ; BE-NEXT:    sub v0.2s, v0.2s, v2.2s
 ; BE-NEXT:    st1 { v0.2s }, [x8]
 ; BE-NEXT:    ret