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mshockwavemshockwave
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fixup! Use the new feature name
1 parent 1bb648e commit 879a642

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3 files changed

+21
-21
lines changed

3 files changed

+21
-21
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrPredicates.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,9 +14,9 @@
1414
// otherwise.
1515
def VLDSX0Pred : MCSchedPredicate<CheckRegOperand<3, X0>>;
1616

17-
// This scheduling predicate is true when subtarget feature TuneHasThrottledVecFP64
17+
// This scheduling predicate is true when subtarget feature TuneHasSingleElementVecFP64
1818
// is enabled.
19-
def ThrottledVecFP64SchedPred : FeatureSchedPredicate<TuneHasThrottledVecFP64>;
19+
def SingleElementVecFP64SchedPred : FeatureSchedPredicate<TuneHasSingleElementVecFP64>;
2020

2121
// Returns true if this is the sext.w pattern, addiw rd, rs1, 0.
2222
def isSEXT_W

‎llvm/lib/Target/RISCV/RISCVProcessors.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -339,7 +339,7 @@ def SIFIVE_X390 : RISCVProcessorModel<"sifive-x390",
339339
FeatureVendorXSiFivecdiscarddlone,
340340
FeatureVendorXSiFivecflushdlone],
341341
!listconcat(SiFiveIntelligenceTuneFeatures,
342-
[TuneHasThrottledVecFP64])>;
342+
[TuneHasSingleElementVecFP64])>;
343343

344344
defvar SiFiveP400TuneFeatures = [TuneNoDefaultUnroll,
345345
TuneConditionalCompressedMoveFusion,

‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -833,33 +833,33 @@ multiclass SiFive7WriteResBase<int VLEN,
833833
foreach sew = SchedSEWSet<mx, isF=1>.val in {
834834
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
835835
if !eq(sew, 64) then {
836-
defvar ThrottledCycles = SiFive7GetCyclesOnePerElement<mx, sew, VLEN>.c;
836+
defvar SingleElementCycles = SiFive7GetCyclesOnePerElement<mx, sew, VLEN>.c;
837837
foreach SchedWriteName = ["WriteVFALUV", "WriteVFALUF", "WriteVFMulV", "WriteVFMulF",
838838
"WriteVFMulAddV", "WriteVFMulAddF"] in
839-
defm : LMULSEWWriteResMXSEWVariant<SchedWriteName, ThrottledVecFP64SchedPred,
839+
defm : LMULSEWWriteResMXSEWVariant<SchedWriteName, SingleElementVecFP64SchedPred,
840840
// Predicated
841-
[VCQ, VA1], ThrottledCycles, [0, 1], [1, !add(1, ThrottledCycles)],
841+
[VCQ, VA1], SingleElementCycles, [0, 1], [1, !add(1, SingleElementCycles)],
842842
// Not Predicated
843843
[VCQ, VA1OrVA2], 8, [0, 1], [1, !add(1, SiFive7GetCyclesDefault<mx>.c)],
844844
mx, sew, IsWorstCase>;
845845
foreach SchedWriteName = ["WriteVFRecpV", "WriteVFCvtIToFV"] in
846-
defm : LMULSEWWriteResMXSEWVariant<SchedWriteName, ThrottledVecFP64SchedPred,
846+
defm : LMULSEWWriteResMXSEWVariant<SchedWriteName, SingleElementVecFP64SchedPred,
847847
// Predicated
848-
[VCQ, VA1], ThrottledCycles, [0, 1], [1, !add(1, ThrottledCycles)],
848+
[VCQ, VA1], SingleElementCycles, [0, 1], [1, !add(1, SingleElementCycles)],
849849
// Not Predicated
850850
[VCQ, VA1], 8, [0, 1], [1, !add(1, SiFive7GetCyclesDefault<mx>.c)],
851851
mx, sew, IsWorstCase>;
852852
foreach SchedWriteName = ["WriteVFSgnjV", "WriteVFSgnjF"] in
853-
defm : LMULSEWWriteResMXSEWVariant<SchedWriteName, ThrottledVecFP64SchedPred,
853+
defm : LMULSEWWriteResMXSEWVariant<SchedWriteName, SingleElementVecFP64SchedPred,
854854
// Predicated
855-
[VCQ, VA1], ThrottledCycles, [0, 1], [1, !add(1, ThrottledCycles)],
855+
[VCQ, VA1], SingleElementCycles, [0, 1], [1, !add(1, SingleElementCycles)],
856856
// Not Predicated
857857
[VCQ, VA1OrVA2], 4, [0, 1], [1, !add(1, SiFive7GetCyclesDefault<mx>.c)],
858858
mx, sew, IsWorstCase>;
859859
foreach SchedWriteName = ["WriteVFMinMaxV", "WriteVFMinMaxF"] in
860-
defm : LMULSEWWriteResMXSEWVariant<SchedWriteName, ThrottledVecFP64SchedPred,
860+
defm : LMULSEWWriteResMXSEWVariant<SchedWriteName, SingleElementVecFP64SchedPred,
861861
// Predicated
862-
[VCQ, VA1], ThrottledCycles, [0, 1], [1, !add(1, ThrottledCycles)],
862+
[VCQ, VA1], SingleElementCycles, [0, 1], [1, !add(1, SingleElementCycles)],
863863
// Not Predicated
864864
[VCQ, VA1], 4, [0, 1], [1, !add(1, SiFive7GetCyclesDefault<mx>.c)],
865865
mx, sew, IsWorstCase>;
@@ -921,10 +921,10 @@ multiclass SiFive7WriteResBase<int VLEN,
921921
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListW>.c;
922922
defvar DefaultCycles = SiFive7GetCyclesDefault<mx>.c;
923923
if !eq(sew, 32) then {
924-
defvar ThrottledCycles = SiFive7GetCyclesOnePerElement<mx, sew, VLEN>.c;
925-
defm : LMULSEWWriteResMXSEWVariant<"WriteVFWCvtIToFV", ThrottledVecFP64SchedPred,
924+
defvar SingleElementCycles = SiFive7GetCyclesOnePerElement<mx, sew, VLEN>.c;
925+
defm : LMULSEWWriteResMXSEWVariant<"WriteVFWCvtIToFV", SingleElementVecFP64SchedPred,
926926
// Predicated
927-
[VCQ, VA1], 8, [0, 1], [1, !add(1, ThrottledCycles)],
927+
[VCQ, VA1], 8, [0, 1], [1, !add(1, SingleElementCycles)],
928928
// Not Predicated
929929
[VCQ, VA1], 8, [0, 1], [1, !add(1, DefaultCycles)],
930930
mx, sew, IsWorstCase>;
@@ -948,10 +948,10 @@ multiclass SiFive7WriteResBase<int VLEN,
948948
defm : LMULSEWWriteResMXSEW<"WriteVFWMulAddF", [VCQ, VA1OrVA2], mx, sew, IsWorstCase>;
949949
}
950950
if !eq(sew, 32) then {
951-
defvar ThrottledCycles = SiFive7GetCyclesOnePerElement<mx, sew, VLEN>.c;
952-
defm : LMULSEWWriteResMXSEWVariant<"WriteVFWCvtFToFV", ThrottledVecFP64SchedPred,
951+
defvar SingleElementCycles = SiFive7GetCyclesOnePerElement<mx, sew, VLEN>.c;
952+
defm : LMULSEWWriteResMXSEWVariant<"WriteVFWCvtFToFV", SingleElementVecFP64SchedPred,
953953
// Predicated
954-
[VCQ, VA1], 8, [0, 1], [1, !add(1, ThrottledCycles)],
954+
[VCQ, VA1], 8, [0, 1], [1, !add(1, SingleElementCycles)],
955955
// Not Predicated
956956
[VCQ, VA1], 8, [0, 1], [1, !add(1, DefaultCycles)],
957957
mx, sew, IsWorstCase>;
@@ -979,11 +979,11 @@ multiclass SiFive7WriteResBase<int VLEN,
979979
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
980980
defvar DefaultCycles = SiFive7GetCyclesNarrowing<mx>.c;
981981
if !eq(sew, 32) then {
982-
defvar ThrottledCycles = SiFive7GetCyclesOnePerElement<mx, sew, VLEN>.c;
982+
defvar SingleElementCycles = SiFive7GetCyclesOnePerElement<mx, sew, VLEN>.c;
983983
foreach SchedWriteName = ["WriteVFNCvtIToFV", "WriteVFNCvtFToFV"] in
984-
defm : LMULSEWWriteResMXSEWVariant<SchedWriteName, ThrottledVecFP64SchedPred,
984+
defm : LMULSEWWriteResMXSEWVariant<SchedWriteName, SingleElementVecFP64SchedPred,
985985
// Predicated
986-
[VCQ, VA1], 8, [0, 1], [1, !add(1, ThrottledCycles)],
986+
[VCQ, VA1], 8, [0, 1], [1, !add(1, SingleElementCycles)],
987987
// Not Predicated
988988
[VCQ, VA1], 8, [0, 1], [1, !add(1, DefaultCycles)],
989989
mx, sew, IsWorstCase>;

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