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[RISCV][IA] Precommit tests for deinterleaveN of masked.load
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‎llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll

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@@ -538,3 +538,164 @@ define { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x
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%res7 = insertvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } %res6, <vscale x 8 x i8> %t7, 7
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ret { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } %res7
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}
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define {<vscale x 16 x i8>, <vscale x 16 x i8>} @masked_load_factor2(ptr %p) {
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; CHECK-LABEL: masked_load_factor2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl4r.v v12, (a0)
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; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v12, 0
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; CHECK-NEXT: vnsrl.wi v10, v12, 8
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; CHECK-NEXT: ret
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%vec = call <vscale x 32 x i8> @llvm.masked.load(ptr %p, i32 4, <vscale x 32 x i1> splat (i1 true), <vscale x 32 x i8> poison)
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%deinterleaved.results = call {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> %vec)
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ret {<vscale x 16 x i8>, <vscale x 16 x i8>} %deinterleaved.results
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}
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define {<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>} @masked_loat_factor4(ptr %p) {
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; CHECK-LABEL: masked_loat_factor4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a1, a1, 2
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; CHECK-NEXT: sub sp, sp, a1
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 4 * vlenb
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; CHECK-NEXT: vl4r.v v8, (a0)
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; CHECK-NEXT: addi a0, sp, 16
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; CHECK-NEXT: vs4r.v v8, (a0)
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; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
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; CHECK-NEXT: vlseg4e8.v v8, (a0)
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a0, a0, 2
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; CHECK-NEXT: add sp, sp, a0
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; CHECK-NEXT: .cfi_def_cfa sp, 16
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: .cfi_def_cfa_offset 0
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; CHECK-NEXT: ret
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%vec = call <vscale x 32 x i8> @llvm.masked.load(ptr %p, i32 4, <vscale x 32 x i1> splat (i1 true), <vscale x 32 x i8> poison)
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%deinterleaved.results = call {<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>} @llvm.vector.deinterleave4.nxv32i8(<vscale x 32 x i8> %vec)
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ret {<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>} %deinterleaved.results
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}
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define {<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>} @masked_loat_factor4_mask(ptr %p, <vscale x 8 x i1> %mask) {
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; CHECK-LABEL: masked_loat_factor4_mask:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a1, a1, 3
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; CHECK-NEXT: sub sp, sp, a1
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
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; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: addi a1, sp, 16
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; CHECK-NEXT: csrr a2, vlenb
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; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
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; CHECK-NEXT: add a3, a1, a2
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; CHECK-NEXT: vmv.v.v v9, v8
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; CHECK-NEXT: srli a4, a2, 2
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; CHECK-NEXT: vmv.v.v v10, v8
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; CHECK-NEXT: srli a5, a2, 3
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; CHECK-NEXT: vmv.v.v v11, v8
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; CHECK-NEXT: vsseg4e8.v v8, (a1)
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; CHECK-NEXT: vl1r.v v8, (a1)
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; CHECK-NEXT: add a1, a4, a5
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; CHECK-NEXT: vl1r.v v9, (a3)
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; CHECK-NEXT: add a3, a3, a2
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; CHECK-NEXT: add a2, a3, a2
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; CHECK-NEXT: vl1r.v v10, (a3)
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; CHECK-NEXT: vl1r.v v11, (a2)
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; CHECK-NEXT: vmsne.vi v9, v9, 0
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; CHECK-NEXT: vmsne.vi v0, v8, 0
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; CHECK-NEXT: vmsne.vi v8, v10, 0
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; CHECK-NEXT: vmsne.vi v10, v11, 0
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; CHECK-NEXT: vsetvli zero, a4, e8, mf2, tu, ma
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; CHECK-NEXT: vslideup.vx v0, v9, a5
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; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, ma
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; CHECK-NEXT: vslideup.vx v0, v8, a4
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; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
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; CHECK-NEXT: vslideup.vx v0, v10, a1
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; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0), v0.t
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a0, a0, 2
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; CHECK-NEXT: add a0, sp, a0
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; CHECK-NEXT: addi a0, a0, 16
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; CHECK-NEXT: vs4r.v v8, (a0)
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; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
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; CHECK-NEXT: vlseg4e8.v v8, (a0)
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a0, a0, 3
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; CHECK-NEXT: add sp, sp, a0
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; CHECK-NEXT: .cfi_def_cfa sp, 16
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: .cfi_def_cfa_offset 0
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; CHECK-NEXT: ret
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%interleaved.mask = tail call <vscale x 32 x i1> @llvm.vector.interleave4.nxv32i1(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask)
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%vec = call <vscale x 32 x i8> @llvm.masked.load(ptr %p, i32 4, <vscale x 32 x i1> %interleaved.mask, <vscale x 32 x i8> poison)
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%deinterleaved.results = call {<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>} @llvm.vector.deinterleave4.nxv32i8(<vscale x 32 x i8> %vec)
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ret {<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>} %deinterleaved.results
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}
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; Negative test - some of the deinterleaved elements might come from the
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; passthru not the load
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define {<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>} @masked_loat_factor4_passthru(ptr %p, <vscale x 8 x i1> %mask, <vscale x 32 x i8> %passthru) {
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; CHECK-LABEL: masked_loat_factor4_passthru:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a1, a1, 3
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; CHECK-NEXT: sub sp, sp, a1
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
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; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
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; CHECK-NEXT: vmv.v.i v12, 0
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; CHECK-NEXT: addi a1, sp, 16
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; CHECK-NEXT: csrr a2, vlenb
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; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
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; CHECK-NEXT: add a3, a1, a2
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; CHECK-NEXT: vmv.v.v v13, v12
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; CHECK-NEXT: srli a4, a2, 2
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; CHECK-NEXT: vmv.v.v v14, v12
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; CHECK-NEXT: srli a5, a2, 3
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; CHECK-NEXT: vmv.v.v v15, v12
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; CHECK-NEXT: vsseg4e8.v v12, (a1)
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; CHECK-NEXT: vl1r.v v12, (a1)
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; CHECK-NEXT: add a1, a4, a5
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; CHECK-NEXT: vl1r.v v13, (a3)
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; CHECK-NEXT: add a3, a3, a2
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; CHECK-NEXT: add a2, a3, a2
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; CHECK-NEXT: vl1r.v v14, (a3)
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; CHECK-NEXT: vl1r.v v15, (a2)
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; CHECK-NEXT: vmsne.vi v13, v13, 0
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; CHECK-NEXT: vmsne.vi v0, v12, 0
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; CHECK-NEXT: vmsne.vi v12, v14, 0
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; CHECK-NEXT: vmsne.vi v14, v15, 0
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; CHECK-NEXT: vsetvli zero, a4, e8, mf2, tu, ma
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; CHECK-NEXT: vslideup.vx v0, v13, a5
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; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, ma
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; CHECK-NEXT: vslideup.vx v0, v12, a4
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; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
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; CHECK-NEXT: vslideup.vx v0, v14, a1
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; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
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; CHECK-NEXT: vle8.v v8, (a0), v0.t
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a0, a0, 2
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; CHECK-NEXT: add a0, sp, a0
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; CHECK-NEXT: addi a0, a0, 16
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; CHECK-NEXT: vs4r.v v8, (a0)
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; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
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; CHECK-NEXT: vlseg4e8.v v8, (a0)
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a0, a0, 3
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; CHECK-NEXT: add sp, sp, a0
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; CHECK-NEXT: .cfi_def_cfa sp, 16
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: .cfi_def_cfa_offset 0
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; CHECK-NEXT: ret
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%interleaved.mask = tail call <vscale x 32 x i1> @llvm.vector.interleave4.nxv32i1(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask)
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%vec = call <vscale x 32 x i8> @llvm.masked.load(ptr %p, i32 4, <vscale x 32 x i1> %interleaved.mask, <vscale x 32 x i8> %passthru)
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%deinterleaved.results = call {<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>} @llvm.vector.deinterleave4.nxv32i8(<vscale x 32 x i8> %vec)
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ret {<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>} %deinterleaved.results
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}

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