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[RISCV] Add SF_ to SiFive instructions in RISCVGenInstrInfo.inc. NFC
1 parent 0afbf17 commit 87d09bb

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6 files changed

+79
-79
lines changed

6 files changed

+79
-79
lines changed

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3763,9 +3763,9 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
37633763
if (!(MCID.TSFlags & RISCVII::ConstraintMask))
37643764
return false;
37653765

3766-
if (Opcode == RISCV::VC_V_XVW || Opcode == RISCV::VC_V_IVW ||
3767-
Opcode == RISCV::VC_V_FVW || Opcode == RISCV::VC_V_VVW) {
3768-
// Operands Opcode, Dst, uimm, Dst, Rs2, Rs1 for VC_V_XVW.
3766+
if (Opcode == RISCV::SF_VC_V_XVW || Opcode == RISCV::SF_VC_V_IVW ||
3767+
Opcode == RISCV::SF_VC_V_FVW || Opcode == RISCV::SF_VC_V_VVW) {
3768+
// Operands Opcode, Dst, uimm, Dst, Rs2, Rs1 for SF_VC_V_XVW.
37693769
MCRegister VCIXDst = Inst.getOperand(0).getReg();
37703770
SMLoc VCIXDstLoc = Operands[2]->getStartLoc();
37713771
if (MCID.TSFlags & RISCVII::VS1Constraint) {

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -879,32 +879,32 @@ void RISCVDAGToDAGISel::selectSF_VC_X_SE(SDNode *Node) {
879879
auto *LMulSDNode = cast<ConstantSDNode>(Node->getOperand(7));
880880
switch (LMulSDNode->getSExtValue()) {
881881
case 5:
882-
Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoVC_X_SE_MF8
883-
: RISCV::PseudoVC_I_SE_MF8;
882+
Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoSF_VC_X_SE_MF8
883+
: RISCV::PseudoSF_VC_I_SE_MF8;
884884
break;
885885
case 6:
886-
Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoVC_X_SE_MF4
887-
: RISCV::PseudoVC_I_SE_MF4;
886+
Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoSF_VC_X_SE_MF4
887+
: RISCV::PseudoSF_VC_I_SE_MF4;
888888
break;
889889
case 7:
890-
Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoVC_X_SE_MF2
891-
: RISCV::PseudoVC_I_SE_MF2;
890+
Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoSF_VC_X_SE_MF2
891+
: RISCV::PseudoSF_VC_I_SE_MF2;
892892
break;
893893
case 0:
894-
Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoVC_X_SE_M1
895-
: RISCV::PseudoVC_I_SE_M1;
894+
Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoSF_VC_X_SE_M1
895+
: RISCV::PseudoSF_VC_I_SE_M1;
896896
break;
897897
case 1:
898-
Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoVC_X_SE_M2
899-
: RISCV::PseudoVC_I_SE_M2;
898+
Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoSF_VC_X_SE_M2
899+
: RISCV::PseudoSF_VC_I_SE_M2;
900900
break;
901901
case 2:
902-
Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoVC_X_SE_M4
903-
: RISCV::PseudoVC_I_SE_M4;
902+
Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoSF_VC_X_SE_M4
903+
: RISCV::PseudoSF_VC_I_SE_M4;
904904
break;
905905
case 3:
906-
Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoVC_X_SE_M8
907-
: RISCV::PseudoVC_I_SE_M8;
906+
Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoSF_VC_X_SE_M8
907+
: RISCV::PseudoSF_VC_I_SE_M8;
908908
break;
909909
}
910910

‎llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td‎

Lines changed: 55 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -160,10 +160,10 @@ multiclass CustomSiFiveVCIX<string suffix, VCIXType type,
160160
DAGOperand InTyRd, DAGOperand InTyRs2,
161161
DAGOperand InTyRs1> {
162162
let vm = 1 in
163-
defm VC_ # NAME : CustomSiFiveVCIXorVCIF<suffix, type, InTyRd, InTyRs2,
163+
defm SF_VC_ # NAME : CustomSiFiveVCIXorVCIF<suffix, type, InTyRd, InTyRs2,
164164
InTyRs1, 0>;
165165
let vm = 0 in
166-
defm VC_V_ # NAME : CustomSiFiveVCIXorVCIF<suffix, type, VR, InTyRs2,
166+
defm SF_VC_V_ # NAME : CustomSiFiveVCIXorVCIF<suffix, type, VR, InTyRs2,
167167
InTyRs1, 1>;
168168
}
169169

@@ -201,29 +201,29 @@ let Predicates = [HasVendorXSfvcp], mayLoad = 0, mayStore = 0,
201201

202202
let Predicates = [HasVendorXSfvqmaccdod], DecoderNamespace = "XSfvector",
203203
DestEEW = EEWSEWx4, RVVConstraint=VS2Constraint in {
204-
def VQMACCU_2x8x2 : CustomSiFiveVMACC<0b101100, OPMVV, "sf.vqmaccu.2x8x2">;
205-
def VQMACC_2x8x2 : CustomSiFiveVMACC<0b101101, OPMVV, "sf.vqmacc.2x8x2">;
206-
def VQMACCUS_2x8x2 : CustomSiFiveVMACC<0b101110, OPMVV, "sf.vqmaccus.2x8x2">;
207-
def VQMACCSU_2x8x2 : CustomSiFiveVMACC<0b101111, OPMVV, "sf.vqmaccsu.2x8x2">;
204+
def SF_VQMACCU_2x8x2 : CustomSiFiveVMACC<0b101100, OPMVV, "sf.vqmaccu.2x8x2">;
205+
def SF_VQMACC_2x8x2 : CustomSiFiveVMACC<0b101101, OPMVV, "sf.vqmacc.2x8x2">;
206+
def SF_VQMACCUS_2x8x2 : CustomSiFiveVMACC<0b101110, OPMVV, "sf.vqmaccus.2x8x2">;
207+
def SF_VQMACCSU_2x8x2 : CustomSiFiveVMACC<0b101111, OPMVV, "sf.vqmaccsu.2x8x2">;
208208
}
209209

210210
let Predicates = [HasVendorXSfvqmaccqoq], DecoderNamespace = "XSfvector",
211211
DestEEW = EEWSEWx4, RVVConstraint=WidenVNoMask in {
212-
def VQMACCU_4x8x4 : CustomSiFiveVMACC<0b111100, OPMVV, "sf.vqmaccu.4x8x4">;
213-
def VQMACC_4x8x4 : CustomSiFiveVMACC<0b111101, OPMVV, "sf.vqmacc.4x8x4">;
214-
def VQMACCUS_4x8x4 : CustomSiFiveVMACC<0b111110, OPMVV, "sf.vqmaccus.4x8x4">;
215-
def VQMACCSU_4x8x4 : CustomSiFiveVMACC<0b111111, OPMVV, "sf.vqmaccsu.4x8x4">;
212+
def SF_VQMACCU_4x8x4 : CustomSiFiveVMACC<0b111100, OPMVV, "sf.vqmaccu.4x8x4">;
213+
def SF_VQMACC_4x8x4 : CustomSiFiveVMACC<0b111101, OPMVV, "sf.vqmacc.4x8x4">;
214+
def SF_VQMACCUS_4x8x4 : CustomSiFiveVMACC<0b111110, OPMVV, "sf.vqmaccus.4x8x4">;
215+
def SF_VQMACCSU_4x8x4 : CustomSiFiveVMACC<0b111111, OPMVV, "sf.vqmaccsu.4x8x4">;
216216
}
217217

218218
let Predicates = [HasVendorXSfvfwmaccqqq], DecoderNamespace = "XSfvector",
219219
DestEEW = EEWSEWx2, RVVConstraint=WidenVNoMask in {
220-
def VFWMACC_4x4x4 : CustomSiFiveVMACC<0b111100, OPFVV, "sf.vfwmacc.4x4x4">;
220+
def SF_VFWMACC_4x4x4 : CustomSiFiveVMACC<0b111100, OPFVV, "sf.vfwmacc.4x4x4">;
221221
}
222222

223223
let Predicates = [HasVendorXSfvfnrclipxfqf], DecoderNamespace = "XSfvector",
224224
Uses = [FRM, VL, VTYPE] in {
225-
def VFNRCLIP_XU_F_QF : CustomSiFiveVFNRCLIP<0b100010, OPFVF, "sf.vfnrclip.xu.f.qf">;
226-
def VFNRCLIP_X_F_QF : CustomSiFiveVFNRCLIP<0b100011, OPFVF, "sf.vfnrclip.x.f.qf">;
225+
def SF_VFNRCLIP_XU_F_QF : CustomSiFiveVFNRCLIP<0b100010, OPFVF, "sf.vfnrclip.xu.f.qf">;
226+
def SF_VFNRCLIP_X_F_QF : CustomSiFiveVFNRCLIP<0b100011, OPFVF, "sf.vfnrclip.x.f.qf">;
227227
}
228228

229229
class VPseudoVC_X<Operand OpClass, DAGOperand RS1Class> :
@@ -306,14 +306,14 @@ multiclass VPseudoVC_X<LMULInfo m, DAGOperand RS1Class,
306306
Operand OpClass = payload2> {
307307
let VLMul = m.value in {
308308
let Defs = [SF_VCIX_STATE], Uses = [SF_VCIX_STATE] in {
309-
def "PseudoVC_" # NAME # "_SE_" # m.MX
309+
def "PseudoSF_VC_" # NAME # "_SE_" # m.MX
310310
: VPseudoVC_X<OpClass, RS1Class>,
311311
Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>;
312-
def "PseudoVC_V_" # NAME # "_SE_" # m.MX
312+
def "PseudoSF_VC_V_" # NAME # "_SE_" # m.MX
313313
: VPseudoVC_V_X<OpClass, m.vrclass, RS1Class>,
314314
Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;
315315
}
316-
def "PseudoVC_V_" # NAME # "_" # m.MX
316+
def "PseudoSF_VC_V_" # NAME # "_" # m.MX
317317
: VPseudoVC_V_X<OpClass, m.vrclass, RS1Class>,
318318
Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;
319319
}
@@ -323,14 +323,14 @@ multiclass VPseudoVC_XV<LMULInfo m, DAGOperand RS1Class,
323323
Operand OpClass = payload2> {
324324
let VLMul = m.value in {
325325
let Defs = [SF_VCIX_STATE], Uses = [SF_VCIX_STATE] in {
326-
def "PseudoVC_" # NAME # "_SE_" # m.MX
326+
def "PseudoSF_VC_" # NAME # "_SE_" # m.MX
327327
: VPseudoVC_XV<OpClass, m.vrclass, RS1Class>,
328328
Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>;
329-
def "PseudoVC_V_" # NAME # "_SE_" # m.MX
329+
def "PseudoSF_VC_V_" # NAME # "_SE_" # m.MX
330330
: VPseudoVC_V_XV<OpClass, m.vrclass, m.vrclass, RS1Class>,
331331
Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;
332332
}
333-
def "PseudoVC_V_" # NAME # "_" # m.MX
333+
def "PseudoSF_VC_V_" # NAME # "_" # m.MX
334334
: VPseudoVC_V_XV<OpClass, m.vrclass, m.vrclass, RS1Class>,
335335
Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;
336336
}
@@ -340,14 +340,14 @@ multiclass VPseudoVC_XVV<LMULInfo m, DAGOperand RS1Class,
340340
Operand OpClass = payload2> {
341341
let VLMul = m.value in {
342342
let Defs = [SF_VCIX_STATE], Uses = [SF_VCIX_STATE] in {
343-
def "PseudoVC_" # NAME # "_SE_" # m.MX
343+
def "PseudoSF_VC_" # NAME # "_SE_" # m.MX
344344
: VPseudoVC_XVV<OpClass, m.vrclass, m.vrclass, RS1Class>,
345345
Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>;
346-
def "PseudoVC_V_" # NAME # "_SE_" # m.MX
346+
def "PseudoSF_VC_V_" # NAME # "_SE_" # m.MX
347347
: VPseudoVC_V_XVV<OpClass, m.vrclass, m.vrclass, RS1Class>,
348348
Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;
349349
}
350-
def "PseudoVC_V_" # NAME # "_" # m.MX
350+
def "PseudoSF_VC_V_" # NAME # "_" # m.MX
351351
: VPseudoVC_V_XVV<OpClass, m.vrclass, m.vrclass, RS1Class>,
352352
Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;
353353
}
@@ -357,15 +357,15 @@ multiclass VPseudoVC_XVW<LMULInfo m, DAGOperand RS1Class,
357357
Operand OpClass = payload2> {
358358
let VLMul = m.value in {
359359
let Defs = [SF_VCIX_STATE], Uses = [SF_VCIX_STATE] in
360-
def "PseudoVC_" # NAME # "_SE_" # m.MX
360+
def "PseudoSF_VC_" # NAME # "_SE_" # m.MX
361361
: VPseudoVC_XVV<OpClass, m.wvrclass, m.vrclass, RS1Class>,
362362
Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>;
363363
let Constraints = "@earlyclobber $rd, $rd = $rs3" in {
364364
let Defs = [SF_VCIX_STATE], Uses = [SF_VCIX_STATE] in
365-
def "PseudoVC_V_" # NAME # "_SE_" # m.MX
365+
def "PseudoSF_VC_V_" # NAME # "_SE_" # m.MX
366366
: VPseudoVC_V_XVV<OpClass, m.wvrclass, m.vrclass, RS1Class>,
367367
Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;
368-
def "PseudoVC_V_" # NAME # "_" # m.MX
368+
def "PseudoSF_VC_V_" # NAME # "_" # m.MX
369369
: VPseudoVC_V_XVV<OpClass, m.wvrclass, m.vrclass, RS1Class>,
370370
Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;
371371
}
@@ -435,26 +435,26 @@ let Predicates = [HasVendorXSfvcp] in {
435435
}
436436

437437
let Predicates = [HasVendorXSfvqmaccdod] in {
438-
defm VQMACCU_2x8x2 : VPseudoSiFiveVQMACCDOD;
439-
defm VQMACC_2x8x2 : VPseudoSiFiveVQMACCDOD;
440-
defm VQMACCUS_2x8x2 : VPseudoSiFiveVQMACCDOD;
441-
defm VQMACCSU_2x8x2 : VPseudoSiFiveVQMACCDOD;
438+
defm SF_VQMACCU_2x8x2 : VPseudoSiFiveVQMACCDOD;
439+
defm SF_VQMACC_2x8x2 : VPseudoSiFiveVQMACCDOD;
440+
defm SF_VQMACCUS_2x8x2 : VPseudoSiFiveVQMACCDOD;
441+
defm SF_VQMACCSU_2x8x2 : VPseudoSiFiveVQMACCDOD;
442442
}
443443

444444
let Predicates = [HasVendorXSfvqmaccqoq] in {
445-
defm VQMACCU_4x8x4 : VPseudoSiFiveVQMACCQOQ;
446-
defm VQMACC_4x8x4 : VPseudoSiFiveVQMACCQOQ;
447-
defm VQMACCUS_4x8x4 : VPseudoSiFiveVQMACCQOQ;
448-
defm VQMACCSU_4x8x4 : VPseudoSiFiveVQMACCQOQ;
445+
defm SF_VQMACCU_4x8x4 : VPseudoSiFiveVQMACCQOQ;
446+
defm SF_VQMACC_4x8x4 : VPseudoSiFiveVQMACCQOQ;
447+
defm SF_VQMACCUS_4x8x4 : VPseudoSiFiveVQMACCQOQ;
448+
defm SF_VQMACCSU_4x8x4 : VPseudoSiFiveVQMACCQOQ;
449449
}
450450

451451
let Predicates = [HasVendorXSfvfwmaccqqq] in {
452-
defm VFWMACC_4x4x4 : VPseudoSiFiveVFWMACC;
452+
defm SF_VFWMACC_4x4x4 : VPseudoSiFiveVFWMACC;
453453
}
454454

455455
let Predicates = [HasVendorXSfvfnrclipxfqf] in {
456-
defm VFNRCLIP_XU_F_QF : VPseudoSiFiveVFNRCLIP;
457-
defm VFNRCLIP_X_F_QF : VPseudoSiFiveVFNRCLIP;
456+
defm SF_VFNRCLIP_XU_F_QF : VPseudoSiFiveVFNRCLIP;
457+
defm SF_VFNRCLIP_X_F_QF : VPseudoSiFiveVFNRCLIP;
458458
}
459459

460460
// SDNode
@@ -660,11 +660,11 @@ class VPatVC_V_OP3<string intrinsic_name,
660660
multiclass VPatVC_X<string intrinsic_suffix, string instruction_suffix,
661661
VTypeInfo vti, ValueType type, DAGOperand kind> {
662662
def : VPatVC_V_OP3_ISD<!cast<SDPatternOperator>("sf_vc_v_" # intrinsic_suffix # "_se"),
663-
"PseudoVC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX,
663+
"PseudoSF_VC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX,
664664
vti.Vector, XLenVT, type, vti.Log2SEW,
665665
payload5, kind>;
666666
def : VPatVC_V_OP3<"int_riscv_sf_vc_v_" # intrinsic_suffix,
667-
"PseudoVC_V_" # instruction_suffix # "_" # vti.LMul.MX,
667+
"PseudoSF_VC_V_" # instruction_suffix # "_" # vti.LMul.MX,
668668
vti.Vector, XLenVT, type, vti.Log2SEW,
669669
payload5, kind>;
670670
}
@@ -673,15 +673,15 @@ multiclass VPatVC_XV<string intrinsic_suffix, string instruction_suffix,
673673
VTypeInfo vti, ValueType type, DAGOperand kind,
674674
Operand op1_kind = payload2> {
675675
def : VPatVC_OP4_ISD<!cast<SDPatternOperator>("sf_vc_" # intrinsic_suffix # "_se"),
676-
"PseudoVC_" # instruction_suffix # "_SE_" # vti.LMul.MX,
676+
"PseudoSF_VC_" # instruction_suffix # "_SE_" # vti.LMul.MX,
677677
XLenVT, vti.Vector, type, vti.Log2SEW,
678678
payload5, vti.RegClass, kind, op1_kind>;
679679
def : VPatVC_V_OP3_ISD<!cast<SDPatternOperator>("sf_vc_v_" # intrinsic_suffix # "_se"),
680-
"PseudoVC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX,
680+
"PseudoSF_VC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX,
681681
vti.Vector, vti.Vector, type, vti.Log2SEW,
682682
vti.RegClass, kind, op1_kind>;
683683
def : VPatVC_V_OP3<"int_riscv_sf_vc_v_" # intrinsic_suffix,
684-
"PseudoVC_V_" # instruction_suffix # "_" # vti.LMul.MX,
684+
"PseudoSF_VC_V_" # instruction_suffix # "_" # vti.LMul.MX,
685685
vti.Vector, vti.Vector, type, vti.Log2SEW,
686686
vti.RegClass, kind, op1_kind>;
687687
}
@@ -690,15 +690,15 @@ multiclass VPatVC_XVV<string intrinsic_suffix, string instruction_suffix,
690690
VTypeInfo wti, VTypeInfo vti, ValueType type, DAGOperand kind,
691691
Operand op1_kind = payload2> {
692692
def : VPatVC_OP4_ISD<!cast<SDPatternOperator>("sf_vc_" # intrinsic_suffix # "_se"),
693-
"PseudoVC_" # instruction_suffix # "_SE_" # vti.LMul.MX,
693+
"PseudoSF_VC_" # instruction_suffix # "_SE_" # vti.LMul.MX,
694694
wti.Vector, vti.Vector, type, vti.Log2SEW,
695695
wti.RegClass, vti.RegClass, kind, op1_kind>;
696696
def : VPatVC_V_OP4_ISD<!cast<SDPatternOperator>("sf_vc_v_" # intrinsic_suffix # "_se"),
697-
"PseudoVC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX,
697+
"PseudoSF_VC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX,
698698
wti.Vector, wti.Vector, vti.Vector, type, vti.Log2SEW,
699699
wti.RegClass, vti.RegClass, kind, op1_kind>;
700700
def : VPatVC_V_OP4<"int_riscv_sf_vc_v_" # intrinsic_suffix,
701-
"PseudoVC_V_" # instruction_suffix # "_" # vti.LMul.MX,
701+
"PseudoSF_VC_V_" # instruction_suffix # "_" # vti.LMul.MX,
702702
wti.Vector, wti.Vector, vti.Vector, type, vti.Log2SEW,
703703
wti.RegClass, vti.RegClass, kind, op1_kind>;
704704
}
@@ -810,26 +810,26 @@ let Predicates = [HasVendorXSfvcp] in {
810810
}
811811

812812
let Predicates = [HasVendorXSfvqmaccdod] in {
813-
defm : VPatVQMACCDOD<"vqmaccu_2x8x2", "VQMACCU", "2x8x2">;
814-
defm : VPatVQMACCDOD<"vqmacc_2x8x2", "VQMACC", "2x8x2">;
815-
defm : VPatVQMACCDOD<"vqmaccus_2x8x2", "VQMACCUS", "2x8x2">;
816-
defm : VPatVQMACCDOD<"vqmaccsu_2x8x2", "VQMACCSU", "2x8x2">;
813+
defm : VPatVQMACCDOD<"vqmaccu_2x8x2", "SF_VQMACCU", "2x8x2">;
814+
defm : VPatVQMACCDOD<"vqmacc_2x8x2", "SF_VQMACC", "2x8x2">;
815+
defm : VPatVQMACCDOD<"vqmaccus_2x8x2", "SF_VQMACCUS", "2x8x2">;
816+
defm : VPatVQMACCDOD<"vqmaccsu_2x8x2", "SF_VQMACCSU", "2x8x2">;
817817
}
818818

819819
let Predicates = [HasVendorXSfvqmaccqoq] in {
820-
defm : VPatVQMACCQOQ<"vqmaccu_4x8x4", "VQMACCU", "4x8x4">;
821-
defm : VPatVQMACCQOQ<"vqmacc_4x8x4", "VQMACC", "4x8x4">;
822-
defm : VPatVQMACCQOQ<"vqmaccus_4x8x4", "VQMACCUS", "4x8x4">;
823-
defm : VPatVQMACCQOQ<"vqmaccsu_4x8x4", "VQMACCSU", "4x8x4">;
820+
defm : VPatVQMACCQOQ<"vqmaccu_4x8x4", "SF_VQMACCU", "4x8x4">;
821+
defm : VPatVQMACCQOQ<"vqmacc_4x8x4", "SF_VQMACC", "4x8x4">;
822+
defm : VPatVQMACCQOQ<"vqmaccus_4x8x4", "SF_VQMACCUS", "4x8x4">;
823+
defm : VPatVQMACCQOQ<"vqmaccsu_4x8x4", "SF_VQMACCSU", "4x8x4">;
824824
}
825825

826826
let Predicates = [HasVendorXSfvfwmaccqqq] in {
827-
defm : VPatVFWMACC<"vfwmacc_4x4x4", "VFWMACC", "4x4x4">;
827+
defm : VPatVFWMACC<"vfwmacc_4x4x4", "SF_VFWMACC", "4x4x4">;
828828
}
829829

830830
let Predicates = [HasVendorXSfvfnrclipxfqf] in {
831-
defm : VPatVFNRCLIP<"vfnrclip_xu_f_qf", "VFNRCLIP_XU_F_QF">;
832-
defm : VPatVFNRCLIP<"vfnrclip_x_f_qf", "VFNRCLIP_X_F_QF">;
831+
defm : VPatVFNRCLIP<"vfnrclip_xu_f_qf", "SF_VFNRCLIP_XU_F_QF">;
832+
defm : VPatVFNRCLIP<"vfnrclip_x_f_qf", "SF_VFNRCLIP_X_F_QF">;
833833
}
834834

835835
let Predicates = [HasVendorXSiFivecdiscarddlone] in {

‎llvm/test/CodeGen/RISCV/rvv/copyprop.mir‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ body: |
4747
%22:vr = PseudoVMSNE_VI_M1 %3, 0, 1, 6 /* e64 */
4848
%23:vmv0 = COPY %22
4949
%25:vrnov0 = PseudoVMERGE_VIM_M1 undef $noreg, %17, -1, %23, 1, 6 /* e64 */
50-
%29:vr = PseudoVC_V_X_SE_M1 3, 31, %2, 1, 6 /* e64 */, implicit-def dead $sf_vcix_state, implicit $sf_vcix_state
50+
%29:vr = PseudoSF_VC_V_X_SE_M1 3, 31, %2, 1, 6 /* e64 */, implicit-def dead $sf_vcix_state, implicit $sf_vcix_state
5151
%30:vr = PseudoVMV_V_I_M1 undef $noreg, 0, 1, 6 /* e64 */, 0
5252
BGEU %1, $x0, %bb.2
5353

‎llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -290,10 +290,10 @@ body: |
290290
; CHECK: liveins: $x2, $x10, $v8, $v13, $v4m4, $v16m4
291291
; CHECK-NEXT: {{ $}}
292292
; CHECK-NEXT: $x0 = PseudoVSETVLI $x10, 66 /* e8, m4, ta, mu */, implicit-def $vl, implicit-def $vtype
293-
; CHECK-NEXT: early-clobber $v4m4 = PseudoVQMACCUS_2x8x2_M4 renamable $v4m4, killed renamable $v13, killed renamable $v16m4, $noreg, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
293+
; CHECK-NEXT: early-clobber $v4m4 = PseudoSF_VQMACCUS_2x8x2_M4 renamable $v4m4, killed renamable $v13, killed renamable $v16m4, $noreg, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
294294
; CHECK-NEXT: $v16m4 = PseudoVMV_V_V_M4 undef $v16m4, $v4m4, $noreg, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
295295
$x0 = PseudoVSETVLI $x10, 66, implicit-def $vl, implicit-def $vtype
296-
early-clobber $v4m4 = PseudoVQMACCUS_2x8x2_M4 renamable $v4m4, killed renamable $v13, killed renamable $v16m4, $noreg, 3, 1, implicit $vl, implicit $vtype
296+
early-clobber $v4m4 = PseudoSF_VQMACCUS_2x8x2_M4 renamable $v4m4, killed renamable $v13, killed renamable $v16m4, $noreg, 3, 1, implicit $vl, implicit $vtype
297297
$v16m4 = COPY renamable $v4m4
298298
...
299299
---
@@ -306,10 +306,10 @@ body: |
306306
; CHECK: liveins: $x2, $x10, $v8, $v13, $v4m4, $v16m2
307307
; CHECK-NEXT: {{ $}}
308308
; CHECK-NEXT: $x0 = PseudoVSETVLI $x10, 65 /* e8, m2, ta, mu */, implicit-def $vl, implicit-def $vtype
309-
; CHECK-NEXT: early-clobber $v4m4 = PseudoVQMACCUS_4x8x4_M2 renamable $v4m4, killed renamable $v13, killed renamable $v16m2, $noreg, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
309+
; CHECK-NEXT: early-clobber $v4m4 = PseudoSF_VQMACCUS_4x8x4_M2 renamable $v4m4, killed renamable $v13, killed renamable $v16m2, $noreg, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
310310
; CHECK-NEXT: $v16m4 = VMV4R_V $v4m4, implicit $vtype
311311
$x0 = PseudoVSETVLI $x10, 65, implicit-def $vl, implicit-def $vtype
312-
early-clobber $v4m4 = PseudoVQMACCUS_4x8x4_M2 renamable $v4m4, killed renamable $v13, killed renamable $v16m2, $noreg, 3, 1, implicit $vl, implicit $vtype
312+
early-clobber $v4m4 = PseudoSF_VQMACCUS_4x8x4_M2 renamable $v4m4, killed renamable $v13, killed renamable $v16m2, $noreg, 3, 1, implicit $vl, implicit $vtype
313313
$v16m4 = COPY renamable $v4m4
314314
...
315315
---

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