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Clear instances of cycles-1=0, add tests
1 parent 2179e4c commit 88279d3

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13 files changed

+8911
-79
lines changed

13 files changed

+8911
-79
lines changed

‎llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td‎

Lines changed: 23 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -129,7 +129,7 @@ let BufferSize = 16 in {
129129
// Vector
130130
def AscalonVA : ProcResource<1>;
131131
def AscalonVB : ProcResource<1>;
132-
def AscalonV : ProcResGroup<[AscalonFPA, AscalonFPB]>;
132+
def AscalonV : ProcResGroup<[AscalonVA, AscalonVB]>;
133133
}
134134

135135

@@ -540,7 +540,7 @@ foreach mx = SchedMxList in {
540540
foreach mx = SchedMxList in {
541541
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
542542
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
543-
let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
543+
let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
544544
defm "" : LMULWriteResMX<"WriteVSALUV", [AscalonFX, AscalonV], mx, IsWorstCase>;
545545
defm "" : LMULWriteResMX<"WriteVSALUX", [AscalonFX, AscalonV], mx, IsWorstCase>;
546546
defm "" : LMULWriteResMX<"WriteVSALUI", [AscalonFX, AscalonV], mx, IsWorstCase>;
@@ -557,7 +557,7 @@ foreach mx = SchedMxList in {
557557
foreach mx = SchedMxListW in {
558558
defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;
559559
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;
560-
let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
560+
let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
561561
defm "" : LMULWriteResMX<"WriteVNClipV", [AscalonFX, AscalonV], mx, IsWorstCase>;
562562
defm "" : LMULWriteResMX<"WriteVNClipX", [AscalonFX, AscalonV], mx, IsWorstCase>;
563563
defm "" : LMULWriteResMX<"WriteVNClipI", [AscalonFX, AscalonV], mx, IsWorstCase>;
@@ -609,7 +609,7 @@ def : ReadAdvance<ReadVST8R, 0>;
609609
foreach mx = SchedMxList in {
610610
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
611611
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
612-
let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
612+
let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
613613
defm "" : LMULWriteResMX<"WriteVIALUV", [AscalonFX, AscalonV], mx, IsWorstCase>;
614614
defm "" : LMULWriteResMX<"WriteVIALUX", [AscalonFX, AscalonV], mx, IsWorstCase>;
615615
defm "" : LMULWriteResMX<"WriteVIALUI", [AscalonFX, AscalonV], mx, IsWorstCase>;
@@ -642,15 +642,15 @@ foreach mx = SchedMxList in {
642642
foreach mx = SchedMxList in {
643643
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
644644
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
645-
let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
645+
let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
646646
defm "" : LMULWriteResMX<"WriteVExtV", [AscalonFX, AscalonV], mx, IsWorstCase>;
647647
}
648648
}
649649
foreach mx = SchedMxList in {
650650
foreach sew = SchedSEWSet<mx>.val in {
651651
defvar Cycles = AscalonGetCyclesDivOrSqrt<mx, sew>.c;
652652
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
653-
let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
653+
let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
654654
defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [AscalonFX, AscalonV], mx, sew, IsWorstCase>;
655655
defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [AscalonFX, AscalonV], mx, sew, IsWorstCase>;
656656
}
@@ -661,7 +661,7 @@ foreach mx = SchedMxList in {
661661
foreach mx = SchedMxListW in {
662662
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
663663
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;
664-
let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
664+
let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
665665
defm "" : LMULWriteResMX<"WriteVIWALUV", [AscalonFX, AscalonV], mx, IsWorstCase>;
666666
defm "" : LMULWriteResMX<"WriteVIWALUX", [AscalonFX, AscalonV], mx, IsWorstCase>;
667667
defm "" : LMULWriteResMX<"WriteVIWALUI", [AscalonFX, AscalonV], mx, IsWorstCase>;
@@ -675,7 +675,7 @@ foreach mx = SchedMxListW in {
675675
foreach mx = SchedMxListW in {
676676
defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;
677677
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;
678-
let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
678+
let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
679679
defm "" : LMULWriteResMX<"WriteVNShiftV", [AscalonFX, AscalonV], mx, IsWorstCase>;
680680
defm "" : LMULWriteResMX<"WriteVNShiftX", [AscalonFX, AscalonV], mx, IsWorstCase>;
681681
defm "" : LMULWriteResMX<"WriteVNShiftI", [AscalonFX, AscalonV], mx, IsWorstCase>;
@@ -687,7 +687,7 @@ foreach mx = SchedMxListF in {
687687
foreach sew = SchedSEWSet<mx, isF=1>.val in {
688688
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
689689
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
690-
let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
690+
let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
691691
defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
692692
defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
693693
defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
@@ -706,15 +706,11 @@ foreach mx = SchedMxListF in {
706706
foreach mx = SchedMxList in {
707707
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
708708
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
709-
let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
709+
let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
710710
defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [AscalonFPA, AscalonV], mx, IsWorstCase>;
711-
}
712-
let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
713711
defm "" : LMULWriteResMX<"WriteVFClassV", [AscalonFP, AscalonV], mx, IsWorstCase>;
714712
defm "" : LMULWriteResMX<"WriteVFMergeV", [AscalonFP, AscalonV], mx, IsWorstCase>;
715713
defm "" : LMULWriteResMX<"WriteVFMovV", [AscalonFP, AscalonV], mx, IsWorstCase>;
716-
}
717-
let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
718714
defm "" : LMULWriteResMX<"WriteVFCmpV", [AscalonFP, AscalonV], mx, IsWorstCase>;
719715
defm "" : LMULWriteResMX<"WriteVFCmpF", [AscalonFP, AscalonV], mx, IsWorstCase>;
720716
}
@@ -723,7 +719,7 @@ foreach mx = SchedMxListF in {
723719
foreach sew = SchedSEWSet<mx, isF=1>.val in {
724720
defvar Cycles = AscalonGetCyclesDivOrSqrt<mx, sew>.c;
725721
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
726-
let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
722+
let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
727723
defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
728724
defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
729725
defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
@@ -736,15 +732,15 @@ foreach mx = SchedMxListW in {
736732
foreach sew = SchedSEWSet<mx, isF=0, isWidening=1>.val in {
737733
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
738734
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListW>.c;
739-
let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in
735+
let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in
740736
defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtIToFV", [AscalonFXB, AscalonV], mx, sew, IsWorstCase>;
741737
}
742738
}
743739
foreach mx = SchedMxListFW in {
744740
foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
745741
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
746742
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
747-
let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
743+
let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
748744
defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
749745
defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
750746
defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
@@ -756,22 +752,22 @@ foreach mx = SchedMxListFW in {
756752
}
757753
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
758754
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListFW>.c;
759-
let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in
755+
let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in
760756
defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [AscalonFPA, AscalonV], mx, IsWorstCase>;
761757
}
762758
// Narrowing
763759
foreach mx = SchedMxListW in {
764760
defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;
765761
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;
766-
let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
762+
let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
767763
defm "" : LMULWriteResMX<"WriteVFNCvtFToIV", [AscalonFPA, AscalonV], mx, IsWorstCase>;
768764
}
769765
}
770766
foreach mx = SchedMxListFW in {
771767
foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
772768
defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;
773769
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
774-
let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
770+
let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
775771
defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtIToFV", [AscalonFXB, AscalonV], mx, sew, IsWorstCase>;
776772
defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtFToFV", [AscalonFXB, AscalonV], mx, sew, IsWorstCase>;
777773
}
@@ -783,7 +779,7 @@ foreach mx = SchedMxList in {
783779
foreach sew = SchedSEWSet<mx>.val in {
784780
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
785781
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
786-
let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
782+
let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
787783
defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [AscalonFX, AscalonV],
788784
mx, sew, IsWorstCase>;
789785
defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [AscalonFX, AscalonV],
@@ -796,7 +792,7 @@ foreach mx = SchedMxListWRed in {
796792
foreach sew = SchedSEWSet<mx, 0, 1>.val in {
797793
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
798794
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListWRed>.c;
799-
let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in
795+
let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in
800796
defm "" : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [AscalonFX, AscalonV],
801797
mx, sew, IsWorstCase>;
802798
}
@@ -806,14 +802,14 @@ foreach mx = SchedMxListF in {
806802
foreach sew = SchedSEWSet<mx, 1>.val in {
807803
defvar RedCycles = AscalonGetCyclesDefault<mx>.c;
808804
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
809-
let Latency = RedCycles, ReleaseAtCycles = [1, !sub(RedCycles, 1)] in {
805+
let Latency = RedCycles, ReleaseAtCycles = [1, RedCycles] in {
810806
defm "" : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [AscalonFX, AscalonV],
811807
mx, sew, IsWorstCase>;
812808
defm "" : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From", [AscalonFX, AscalonV],
813809
mx, sew, IsWorstCase>;
814810
}
815811
defvar OrdRedCycles = AscalonGetCyclesLMUL<mx, 18>.c;
816-
let Latency = OrdRedCycles, ReleaseAtCycles = [1, !sub(OrdRedCycles, 1)] in
812+
let Latency = OrdRedCycles, ReleaseAtCycles = [1, OrdRedCycles] in
817813
defm "" : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [AscalonFX, AscalonV],
818814
mx, sew, IsWorstCase>;
819815
}
@@ -823,11 +819,11 @@ foreach mx = SchedMxListFWRed in {
823819
foreach sew = SchedSEWSet<mx, 1, 1>.val in {
824820
defvar RedCycles = AscalonGetCyclesDefault<mx>.c;
825821
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListFWRed, 1>.c;
826-
let Latency = RedCycles, ReleaseAtCycles = [1, !sub(RedCycles, 1)] in
822+
let Latency = RedCycles, ReleaseAtCycles = [1, RedCycles] in
827823
defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedV_From", [AscalonFX, AscalonV],
828824
mx, sew, IsWorstCase>;
829825
defvar OrdRedCycles = AscalonGetCyclesLMUL<mx, 18>.c;
830-
let Latency = OrdRedCycles, ReleaseAtCycles = [1, !sub(OrdRedCycles, 1)] in
826+
let Latency = OrdRedCycles, ReleaseAtCycles = [1, OrdRedCycles] in
831827
defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [AscalonFX, AscalonV],
832828
mx, sew, IsWorstCase>;
833829
}
@@ -848,7 +844,7 @@ foreach mx = SchedMxList in {
848844
foreach mx = SchedMxList in {
849845
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
850846
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
851-
let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
847+
let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
852848
defm "" : LMULWriteResMX<"WriteVIotaV", [AscalonFX, AscalonV], mx, IsWorstCase>;
853849
defm "" : LMULWriteResMX<"WriteVIdxV", [AscalonFX, AscalonV], mx, IsWorstCase>;
854850
}

‎llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fp.s‎

Lines changed: 28 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -47,33 +47,35 @@ fsqrt.d ft2, fa3
4747
# CHECK-NEXT: 1 12 6.00 fsqrt.d ft2, fa3
4848

4949
# CHECK: Resources:
50-
# CHECK-NEXT: [0.0] - AscalonFP
51-
# CHECK-NEXT: [0.1] - AscalonFP
52-
# CHECK-NEXT: [1] - AscalonFXA
53-
# CHECK-NEXT: [2] - AscalonFXB
54-
# CHECK-NEXT: [3.0] - AscalonFXC
55-
# CHECK-NEXT: [3.1] - AscalonFXC
56-
# CHECK-NEXT: [4.0] - AscalonFXD
57-
# CHECK-NEXT: [4.1] - AscalonFXD
58-
# CHECK-NEXT: [5.0] - AscalonLS
59-
# CHECK-NEXT: [5.1] - AscalonLS
60-
# CHECK-NEXT: [5.2] - AscalonLS
50+
# CHECK-NEXT: [0] - AscalonFPA
51+
# CHECK-NEXT: [1] - AscalonFPB
52+
# CHECK-NEXT: [2] - AscalonFXA
53+
# CHECK-NEXT: [3] - AscalonFXB
54+
# CHECK-NEXT: [4.0] - AscalonFXC
55+
# CHECK-NEXT: [4.1] - AscalonFXC
56+
# CHECK-NEXT: [5.0] - AscalonFXD
57+
# CHECK-NEXT: [5.1] - AscalonFXD
58+
# CHECK-NEXT: [6.0] - AscalonLS
59+
# CHECK-NEXT: [6.1] - AscalonLS
60+
# CHECK-NEXT: [6.2] - AscalonLS
61+
# CHECK-NEXT: [7] - AscalonVA
62+
# CHECK-NEXT: [8] - AscalonVB
6163

6264
# CHECK: Resource pressure per iteration:
63-
# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2]
64-
# CHECK-NEXT: 18.00 28.00 - - - - - - - - -
65+
# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]
66+
# CHECK-NEXT: 18.00 28.00 - - - - - - - - - - -
6567

6668
# CHECK: Resource pressure by instruction:
67-
# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] Instructions:
68-
# CHECK-NEXT: - 1.00 - - - - - - - - - fmin.s ft0, fa0, fa1
69-
# CHECK-NEXT: 1.00 - - - - - - - - - - fmax.s ft1, fa0, fa1
70-
# CHECK-NEXT: - 1.00 - - - - - - - - - fmin.d ft2, ft4, ft5
71-
# CHECK-NEXT: 1.00 - - - - - - - - - - fmax.d ft3, ft4, ft5
72-
# CHECK-NEXT: - 1.00 - - - - - - - - - fmadd.s fs0, fs0, fs8, fs9
73-
# CHECK-NEXT: 1.00 - - - - - - - - - - fmsub.s fs1, fs1, fs8, fs9
74-
# CHECK-NEXT: - 1.00 - - - - - - - - - fmul.s fs3, fs3, fs4
75-
# CHECK-NEXT: 7.00 - - - - - - - - - - fdiv.s fs2, fs3, fs4
76-
# CHECK-NEXT: 1.00 - - - - - - - - - - fmul.d ft4, ft4, ft5
77-
# CHECK-NEXT: - 12.00 - - - - - - - - - fdiv.d fs4, fa3, ft5
78-
# CHECK-NEXT: 7.00 - - - - - - - - - - fsqrt.s ft1, fa2
79-
# CHECK-NEXT: - 12.00 - - - - - - - - - fsqrt.d ft2, fa3
69+
# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions:
70+
# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmin.s ft0, fa0, fa1
71+
# CHECK-NEXT: 1.00 - - - - - - - - - - - - fmax.s ft1, fa0, fa1
72+
# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmin.d ft2, ft4, ft5
73+
# CHECK-NEXT: 1.00 - - - - - - - - - - - - fmax.d ft3, ft4, ft5
74+
# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmadd.s fs0, fs0, fs8, fs9
75+
# CHECK-NEXT: 1.00 - - - - - - - - - - - - fmsub.s fs1, fs1, fs8, fs9
76+
# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmul.s fs3, fs3, fs4
77+
# CHECK-NEXT: 7.00 - - - - - - - - - - - - fdiv.s fs2, fs3, fs4
78+
# CHECK-NEXT: 1.00 - - - - - - - - - - - - fmul.d ft4, ft4, ft5
79+
# CHECK-NEXT: - 12.00 - - - - - - - - - - - fdiv.d fs4, fa3, ft5
80+
# CHECK-NEXT: 7.00 - - - - - - - - - - - - fsqrt.s ft1, fa2
81+
# CHECK-NEXT: - 12.00 - - - - - - - - - - - fsqrt.d ft2, fa3

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