[LegalizeVectorOps] Make the AArch64 hack in ExpandFNEG more specific.

Only scalarize single element vectors when vector FSUB is not
supported and scalar FNEG is supported.

Author: topperc

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

@@ -1793,9 +1793,13 @@ SDValue VectorLegalizer::ExpandFNEG(SDNode *Node) {
   EVT VT = Node->getValueType(0);
   EVT IntVT = VT.changeVectorElementTypeToInteger();
 
-  // FIXME: The FSUB check is here to force unrolling v1f64 vectors on AArch64.
-  if (!TLI.isOperationLegalOrCustom(ISD::XOR, IntVT) ||
-      !(TLI.isOperationLegalOrCustom(ISD::FSUB, VT) || VT.isScalableVector()))
+  if (!TLI.isOperationLegalOrCustom(ISD::XOR, IntVT))
+    return SDValue();
+
+  // FIXME: This is to force unrolling v1f64 vectors for AArch64.
+  if (VT.isFixedLengthVector() && VT.getVectorNumElements() == 1 &&
+      !TLI.isOperationLegalOrCustom(ISD::FSUB, VT) &&
+      TLI.isOperationLegal(ISD::FNEG, VT.getVectorElementType()))
     return SDValue();
 
   SDLoc DL(Node);

llvm/test/CodeGen/NVPTX/f16-instructions.ll

@@ -1192,8 +1192,7 @@ define half @test_neg_f16(half noundef %arg) #0 {
 ; CHECK-LABEL: test_neg_f16x2(
 ; CHECK-F16-NOFTZ: neg.f16x2
 ; CHECK-F16-FTZ: neg.ftz.f16x2
-; CHECK-NOF16: xor.b16  	%rs{{.*}}, %rs{{.*}}, -32768
-; CHECK-NOF16: xor.b16  	%rs{{.*}}, %rs{{.*}}, -32768
+; CHECK-NOF16: xor.b32 %r{{.*}}, %r{{.*}}, -2147450880
 define <2 x half> @test_neg_f16x2(<2 x half> noundef %arg) #0 {
   %res = fneg <2 x half> %arg
   ret <2 x half> %res