b

Author: AZero13

llvm/lib/Target/ARM/ARMISelLowering.cpp

@@ -118,6 +118,7 @@ using namespace llvm;
 #define DEBUG_TYPE "arm-isel"
 
 STATISTIC(NumTailCalls, "Number of tail calls");
+STATISTIC(NumOptimizedImms, "Number of times immediates were optimized");
 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
 STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments");
 STATISTIC(NumConstpoolPromoted,
@@ -20154,23 +20155,21 @@ static bool isLegalLogicalImmediate(unsigned Imm, const ARMSubtarget *Subtarget)
   return Imm <= 255;
 }
 
-static bool optimizeLogicalImm(SDValue Op, unsigned Size, unsigned Imm,
-                               const APInt &Demanded,
+static bool optimizeLogicalImm(SDValue Op, unsigned Imm, const APInt &Demanded,
                                TargetLowering::TargetLoweringOpt &TLO,
                                unsigned NewOpc, const ARMSubtarget *Subtarget) {
-  unsigned OldImm = Imm, NewImm, Enc;
-  unsigned Mask = ~0U, OrigMask = Mask;
-  bool Invert = false;
+  unsigned OldImm = Imm, NewImm;
+  unsigned Mask = ~0U;
 
   // Return if the immediate is already all zeros, all ones, a bimm32.
-  if (Imm == 0 || Imm == Mask || isLegalLogicalImmediate(Imm, Subtarget))
+  if (Imm == 0 || Imm == ~0U || isLegalLogicalImmediate(Imm, Subtarget))
     return false;
 
   // bic/orn/eon
   if ((Op.getOpcode() == ISD::AND || (Subtarget->isThumb2() && Op.getOpcode() == ISD::OR)) && isLegalLogicalImmediate(~Imm, Subtarget))
     return false;
 
-  unsigned EltSize = Size;
+  unsigned EltSize = 32;
   unsigned DemandedBits = Demanded.getZExtValue();
 
   // Clear bits that are not demanded.
@@ -20220,7 +20219,7 @@ static bool optimizeLogicalImm(SDValue Op, unsigned Size, unsigned Imm,
   ++NumOptimizedImms;
 
   // Replicate the element across the register width.
-  while (EltSize < Size) {
+  while (EltSize < 32) {
     NewImm |= NewImm << EltSize;
     EltSize *= 2;
   }
@@ -20237,15 +20236,14 @@ static bool optimizeLogicalImm(SDValue Op, unsigned Size, unsigned Imm,
 
   // If the new constant immediate is all-zeros or all-ones, let the target
   // independent DAG combine optimize this node.
-  if (NewImm == 0 || NewImm == OrigMask) {
+  if (NewImm == 0 || NewImm == ~0U) {
     New = TLO.DAG.getNode(Op.getOpcode(), DL, VT, Op.getOperand(0),
                           TLO.DAG.getConstant(NewImm, DL, VT));
     // Otherwise, create a machine node so that target independent DAG combine
     // doesn't undo this optimization.
   } else {
-    SDValue EncConst = TLO.DAG.getTargetConstant(NewImm, DL, VT);
-    New = SDValue(
-        TLO.DAG.getMachineNode(NewOpc, DL, VT, Op.getOperand(0), EncConst), 0);
+    // Temporarily disable this optimization to avoid crashes
+    return false;
   }
 
   return TLO.CombineTo(Op, New);
@@ -20267,11 +20265,52 @@ bool ARMTargetLowering::targetShrinkDemandedConstant(
     return false;
 
   assert(VT == MVT::i32 && "Unexpected integer type");
-  
+
   // Exit early if we demand all bits.
-  if (DemandedBits.popcount == 32)
+  if (DemandedBits.popcount() == 32)
+    return false;
+
+  // Make sure the RHS really is a constant.
+  ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
+  if (!C)
     return false;
 
+  unsigned Mask = C->getZExtValue();
+
+  // If thumb, check for uxth and uxtb masks.
+  if (Subtarget->isThumb1Only() && Op.getOpcode() == ISD::AND) {
+    unsigned Demanded = DemandedBits.getZExtValue();
+    unsigned ShrunkMask = Mask & Demanded;
+    unsigned ExpandedMask = Mask | ~Demanded;
+
+    // If the mask is all zeros, let the target-independent code replace the
+    // result with zero.
+    if (ShrunkMask == 0)
+      return false;
+
+    // If the mask is all ones, erase the AND. (Currently, the
+    // target-independent code won't do this, so we have to do it explicitly to
+    // avoid an infinite loop in obscure cases.)
+    if (ExpandedMask == ~0U)
+      return TLO.CombineTo(Op, Op.getOperand(0));
+    auto IsLegalMask = [ShrunkMask, ExpandedMask](unsigned Mask) -> bool {
+      return (ShrunkMask & Mask) == ShrunkMask && (~ExpandedMask & Mask) == 0;
+    };
+    auto UseMask = [Mask, Op, VT, &TLO](unsigned NewMask) -> bool {
+      if (NewMask == Mask)
+        return true;
+      SDLoc DL(Op);
+      SDValue NewC = TLO.DAG.getConstant(NewMask, DL, VT);
+      SDValue NewOp = TLO.DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), NewC);
+      return TLO.CombineTo(Op, NewOp);
+    };
+
+    if (IsLegalMask(0xFF))
+      return UseMask(0xFF);
+    if (IsLegalMask(0xFFFF))
+      return UseMask(0xFFFF);
+  }
+
   unsigned NewOpc;
   switch (Op.getOpcode()) {
   default:
@@ -20293,13 +20332,7 @@ bool ARMTargetLowering::targetShrinkDemandedConstant(
     break;
   }
 
-  // Make sure the RHS really is a constant.
-  ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
-  if (!C)
-    return false;
-
-  unsigned Imm = C->getZExtValue();
-  return optimizeLogicalImm(Op, Size, Imm, DemandedBits, TLO, NewOpc, Subtarget);
+  return optimizeLogicalImm(Op, Mask, DemandedBits, TLO, NewOpc, Subtarget);
 }
 
 bool ARMTargetLowering::SimplifyDemandedBitsForTargetNode(

llvm/test/CodeGen/ARM/funnel-shift-rot.ll

@@ -19,7 +19,7 @@ declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
 define i8 @rotl_i8_const_shift(i8 %x) {
 ; CHECK-LABEL: rotl_i8_const_shift:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    uxtb r1, r0
+; CHECK-NEXT:    and r1, r0, #224
 ; CHECK-NEXT:    lsl r0, r0, #3
 ; CHECK-NEXT:    orr r0, r0, r1, lsr #5
 ; CHECK-NEXT:    bx lr
@@ -161,8 +161,7 @@ define <4 x i32> @rotl_v4i32_rotl_const_shift(<4 x i32> %x) {
 define i8 @rotr_i8_const_shift(i8 %x) {
 ; CHECK-LABEL: rotr_i8_const_shift:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    uxtb r1, r0
-; CHECK-NEXT:    lsr r1, r1, #3
+; CHECK-NEXT:    ubfx r1, r0, #3, #5
 ; CHECK-NEXT:    orr r0, r1, r0, lsl #5
 ; CHECK-NEXT:    bx lr
   %f = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3)

llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll

@@ -21,9 +21,9 @@ define i1 @scalar_i8_signbit_eq(i8 %x, i8 %y) nounwind {
 ; ARM-LABEL: scalar_i8_signbit_eq:
 ; ARM:       @ %bb.0:
 ; ARM-NEXT:    uxtb r1, r1
-; ARM-NEXT:    lsl r0, r0, r1
+; ARM-NEXT:    mov r2, #128
+; ARM-NEXT:    and r0, r2, r0, lsl r1
 ; ARM-NEXT:    mov r1, #1
-; ARM-NEXT:    uxtb r0, r0
 ; ARM-NEXT:    eor r0, r1, r0, lsr #7
 ; ARM-NEXT:    bx lr
 ;
@@ -42,7 +42,7 @@ define i1 @scalar_i8_signbit_eq(i8 %x, i8 %y) nounwind {
 ; THUMB78-NEXT:    uxtb r1, r1
 ; THUMB78-NEXT:    lsls r0, r1
 ; THUMB78-NEXT:    movs r1, #1
-; THUMB78-NEXT:    uxtb r0, r0
+; THUMB78-NEXT:    and r0, r0, #128
 ; THUMB78-NEXT:    eor.w r0, r1, r0, lsr #7
 ; THUMB78-NEXT:    bx lr
   %t0 = lshr i8 128, %y
@@ -122,9 +122,9 @@ define i1 @scalar_i16_signbit_eq(i16 %x, i16 %y) nounwind {
 ; ARM-LABEL: scalar_i16_signbit_eq:
 ; ARM:       @ %bb.0:
 ; ARM-NEXT:    uxth r1, r1
-; ARM-NEXT:    lsl r0, r0, r1
+; ARM-NEXT:    mov r2, #32768
+; ARM-NEXT:    and r0, r2, r0, lsl r1
 ; ARM-NEXT:    mov r1, #1
-; ARM-NEXT:    uxth r0, r0
 ; ARM-NEXT:    eor r0, r1, r0, lsr #15
 ; ARM-NEXT:    bx lr
 ;
@@ -144,7 +144,7 @@ define i1 @scalar_i16_signbit_eq(i16 %x, i16 %y) nounwind {
 ; THUMB78-NEXT:    uxth r1, r1
 ; THUMB78-NEXT:    lsls r0, r1
 ; THUMB78-NEXT:    movs r1, #1
-; THUMB78-NEXT:    uxth r0, r0
+; THUMB78-NEXT:    and r0, r0, #32768
 ; THUMB78-NEXT:    eor.w r0, r1, r0, lsr #15
 ; THUMB78-NEXT:    bx lr
   %t0 = lshr i16 32768, %y
@@ -862,21 +862,35 @@ define <4 x i1> @vec_4xi32_nonsplat_undef2_eq(<4 x i32> %x, <4 x i32> %y) nounwi
 ;------------------------------------------------------------------------------;
 
 define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind {
-; ARM-LABEL: scalar_i8_signbit_ne:
-; ARM:       @ %bb.0:
-; ARM-NEXT:    uxtb r1, r1
-; ARM-NEXT:    lsl r0, r0, r1
-; ARM-NEXT:    uxtb r0, r0
-; ARM-NEXT:    lsr r0, r0, #7
-; ARM-NEXT:    bx lr
+; ARM6-LABEL: scalar_i8_signbit_ne:
+; ARM6:       @ %bb.0:
+; ARM6-NEXT:    uxtb r1, r1
+; ARM6-NEXT:    mov r2, #128
+; ARM6-NEXT:    and r0, r2, r0, lsl r1
+; ARM6-NEXT:    lsr r0, r0, #7
+; ARM6-NEXT:    bx lr
 ;
-; THUMB-LABEL: scalar_i8_signbit_ne:
-; THUMB:       @ %bb.0:
-; THUMB-NEXT:    uxtb r1, r1
-; THUMB-NEXT:    lsls r0, r1
-; THUMB-NEXT:    uxtb r0, r0
-; THUMB-NEXT:    lsrs r0, r0, #7
-; THUMB-NEXT:    bx lr
+; ARM78-LABEL: scalar_i8_signbit_ne:
+; ARM78:       @ %bb.0:
+; ARM78-NEXT:    uxtb r1, r1
+; ARM78-NEXT:    lsl r0, r0, r1
+; ARM78-NEXT:    ubfx r0, r0, #7, #1
+; ARM78-NEXT:    bx lr
+;
+; THUMB6-LABEL: scalar_i8_signbit_ne:
+; THUMB6:       @ %bb.0:
+; THUMB6-NEXT:    uxtb r1, r1
+; THUMB6-NEXT:    lsls r0, r1
+; THUMB6-NEXT:    uxtb r0, r0
+; THUMB6-NEXT:    lsrs r0, r0, #7
+; THUMB6-NEXT:    bx lr
+;
+; THUMB78-LABEL: scalar_i8_signbit_ne:
+; THUMB78:       @ %bb.0:
+; THUMB78-NEXT:    uxtb r1, r1
+; THUMB78-NEXT:    lsls r0, r1
+; THUMB78-NEXT:    ubfx r0, r0, #7, #1
+; THUMB78-NEXT:    bx lr
   %t0 = lshr i8 128, %y
   %t1 = and i8 %t0, %x
   %res = icmp ne i8 %t1, 0 ;  we are perfectly happy with 'ne' predicate
@@ -1051,3 +1065,5 @@ define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
   %res = icmp eq i8 %t1, 1 ; should be comparing with 0
   ret i1 %res
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; THUMB: {{.*}}