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1 parent 5135dcd commit 88d0751Copy full SHA for 88d0751
llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
@@ -2466,6 +2466,9 @@ SILoadStoreOptimizer::collectMergeableInsts(
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continue;
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if (CI.InstClass == DS_WRITE && CI.IsAGPR) {
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+ LLVM_DEBUG(
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+ dbgs() << "cannot merge ds writes with mixed AGPR and VGPR data\n");
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+
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// FIXME: nothing is illegal in a ds_write2 opcode with two AGPR data
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// operands. However we are reporting that ds_write2 shall have
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// only VGPR data so that machine copy propagation does not
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